Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 47
UG393 (v1.1) April 29, 2010
Chapter 5
Design of Transitions for High-Speed
Signals
Each transition in the channel must be designed to minimize any negative impact on the
link performance. This chapter addresses the interface at either end of a transmission line.
Transmission lines have defined and controlled characteristic impedance along their
length. However, the three-dimensional structures that they interface do not have easily
defined or constant impedance along the signal path. Software tools such as 3D field
solvers are necessary for computing the impedance that a 10 Gb/s signal sees as it passes
through these structures, while 2D field solvers are sufficient for computing transmission
line characteristic impedance.
PCB designers can use the analyses and examples in this chapter to assist the design of
such a channel. Cases not covered in this chapter might need further simulation and
analysis.
Excess Capacitance and Inductance
Most differential transitions are overly capacitive. The P and N paths couple to each other,
increasing capacitance. Many transitions have a frequency response identical to that of a
lumped capacitor over a wide frequency band.
By design, adding inductance cancels this excess capacitance in many cases except when
impacted by density concerns and physical limitations. While techniques such as blind
vias, solder balls on a larger pitch, and very small via pads reduce capacitance, they are not
always feasible in a design.
Time domain reflectometry (TDR) techniques, either through simulation or measurement,
allow the designer to identify excess capacitance or excess inductance in a transition.
Time Domain Reflectometry
To make TDR measurements, a step input is applied to the interconnect. The location and
magnitude of the excess capacitance or inductance that the voltage step experiences as it
traverses the interconnect can be determined through observing the reflected signal.
A shunt capacitance (see Figure 5-1) causes a momentary dip in the impedance, while a
series inductance (see Figure 5-2) causes an impedance discontinuity in the opposite
direction. Td is the propagation delay through the first transmission line segment on the
left. The reflected wave due to the impedance discontinuity takes 2 * Td to return to the
TDR port. If the signal propagation speed through the transmission line is known, the
location of the excess capacitance or inductance along the channel can be calculated.
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