6146/6156 DC Voltage/Current Generators Operation Manual
5.6.1 Status Register
5-20
3. Status Byte Register
The Status Byte Register summarizes the information from the Status Register. This Status Byte
Register's summary is transmitted as a service request to the controller. Consequently, the Status Byte
Register is slightly different from the Status Register in structure. The Status Byte Register is ex-
plained in the following:
The following figure shows the structure of the Status Byte Register.
Figure 5-3 Status Byte Register Structure
The Status Byte Register conforms to the Status Register except for the following three points.
• The summary of the Status Byte Register is written into bit 6 of the Status Byte Register.
• Enable Register's bit 6 is always enabled and cannot be changed.
• Status Byte Register's bit 6 (MSS) writes RQS (service request).
This register responds to a serial poll from the controller.
When responding to the serial poll, bit 0 to 5, bit 7, and RQS of the Status Byte Register are read, after
which RQS is reset to 0. Other bits are not cleared until their factors become 0.
The Status Byte Register, RQS, and MSS can be cleared by executing "*CLS." Accompanying this, the
SRQ line also becomes False.
The following table describes each bit of the Status Byte Register.
Table 5-4 Status Byte Register (STB)
bit Name Description
0 Not in use Always set to 0
1 Not in use Always set to 0
2EAV
Error Available
ON : Set to 1 when error information is stored in Error Queue.
OFF : Set to 0 when Error Queue is read and becomes empty.
3DSB
Device Event Sum-
mary Bit
ON : Set to 1 when any of the DESR incidents occurs and the bit is set to 1, if the
corresponding DESER bit is also 1.
OFF : Set to 0 when DESR is cleared by reading (DSR?).
4MAV
Message Available
ON : Set to 1 when query response data is entered in the output buffer.
OFF : Set to 0 when the output buffer is read and becomes empty.
5ESB
Standard Event Sum-
mary Bit
ON : Set to 1 when any of the SESR incidents occurs and the bit is set to 1, if the
corresponding SESER bit is also 1.
OFF : Set to 0 when SESR is cleared by reading (*ESR?).
6MSS
Master Summary
ON : Set to 1 when any of the STB incidents occurs, if the corresponding SRER
bit is 1.
RQS
Request Service
ON : Set to 1 when MSS is set to 1, and SRQ is generated.
OFF : Set to 0 when STB is read by a serial poll.
7 Not in use Always set to 0
Status Byte Register
Service Request Enable
Register
→ MSS
MSS
RQS
ESB DSB
MAV 2 1
7X54
321
0
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