ANET3910-EN User’s Manual
4.2 Global RAM
SSRAM, shared between the ASP- and BIU-Processors.
4.3 LS BIU Section
The LS-BIU consist of the BIU processor, the STANAG-3838/MIL-STD-1553B
Encoder/Decoder logic to handle the Low Speed Bus protocol, the Trigger-Logic to
handle the Trigger-I/O signals in BC, RT and BM operating modes and a SPI-Flash for
BIU-Processor Boot.
4.3.1 STANAG 3838 Encoder
The STANAG 3838 encoder comprises a Manchester Encoder with full error injection
capability as required by the 'Remote Terminal Production Test Plan'.
4.3.2 STANAG 3838 Decoder
The STANAG 3838 Manchester decoder samples the incoming serial data stream.
The decoder detects the synchronization pattern (Command/Status and Data Sync.),
converts 16 bit Manchester encoded serial data to parallel and receives the parity bit.
The decoder indicates the synchronization pattern and error information (parity error,
Manchester error, framing error) via dedicated bits in an error status register.
4.4 HS BIU Section
The HS-BIU consists of the SoC CPU-Core, the STANAG3910 Encoder/Decoder logic
to handle the High Speed Bus protocol and the Trigger-Logic to handle the HS BM-
Trigger-Output generation.
4.4.1 STANAG 3910 Encoder
The STANAG 3910 encoder comprises a Manchester Encoder with full error injection
capability. The encoder is used to generate faulty (or fault free) message frames on the
bus. The encoder allows to insert protocol errors. Large Data FIFO's are provided within
the encoder to relax the real-time requirements on the high speed bus.
4.4.2 STANAG 3910 Decoder
The Manchester decoder samples the incoming serial data stream. The decoder detects
the Start and End Delimiter Patterns and converts 16 bit Manchester encoded serial
data to parallel and verifies the Frame Check Sequence Word. The decoder indicates
the Error information via dedicated bits in a readable error register. Large Data FIFO's
are provided within the decoder to relax the real-time requirements on the high speed
bus.
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