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AMD Vega 10 - Table 2-3 Maximum Pixel Rates for 4, 2, or 1 Lane(S) at 8.1-Ghz Link Rate

AMD Vega 10
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Note: *Although GPU can support 8.1 Gbps link data rate, in eDP applications, GPU
is validated up to 5.4 Gbps data rate due to unavailability of 8.1 Gbps capable TCONs.
• Supports RGB formats 24, 30, and 36 bpp, as well as 18 bpp RGB for eDP
• Supports YCbCr formats in 4:4:4, 4:2:2, and 4:2:0 and 8, 10, and 12 bits/
component using Rec. 709 and Rec. 2020
• Supports all video modes supported by the display controller that do not
oversubscribe the link bandwidth
• Example of supported pixel rate/resolution support for four lanes at 8.1-
Gbps link rate:
∘ 5120 × 2880 @ 60 Hz, 24 bpp is supported using VESA timings @
938.25 MP/sec
∘ 3840 × 2160 @ 120 Hz, 24 bpp is supported using VESA timings @
1075.804 MP/sec
• Examples of supported pixel-rate/resolution for four lanes at 5.4-Gbps link
rate:
∘ 3840 × 2160 @ 60 Hz, 24 bpp or 30 bpp is supported using VESA
timings @ 533.25 MP/sec
∘ 3840 × 2160 @ 60 Hz, 24 bpp or 30 bpp is supported using CTA
timings @ 594 MP/sec
∘ 4096 × 2160 @ 60 Hz, 24 bpp or 30 bpp is supported using CTA
timings @ 594 MP/sec
∘ 2560 × 1440 @ 144 Hz, 24 bpp is supported using CTA timings @
586.586 MP/sec
• Examples of supported pixel-rate/resolution for two lanes at 5.4-Gbps link
rate:
∘ 2560 × 1600 @ 60 Hz, 24 bpp or 30 bpp is supported using VESA
timings @ 268.5 MP/sec
• The following table shows the maximum pixel rates for four, two, or one
lane(s) at 8.1-GHz link rate.
Table 2–3 Maximum Pixel Rates for 4, 2, or 1 Lane(s) at 8.1-GHz Link Rate
18 bpp 24 bpp 30 bpp 36 bpp
One Lane
360 MP/s 270 MP/s 216 MP/s 180 MP/s
Two Lanes
720 MP/s 540 MP/s 432 MP/s 360 MP/s
Four Lanes
1080 MP/s 1080 MP/s 864 MP/s 720 MP/s
• Embedded DisplayPort (eDP) specific features:
• Supports VESA eDP spec version 1.4
• Supports protected content on eDP via ASSR and HDCP
• Panel Self Refresh (PSR) support as per eDP 1.4 specification for optimal
power reduction when in static screen condition
• AMD FreeSync™ is used as a power-savings feature in eDP applications
Functional Overview 11
© 2017 Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
"Vega 10" Databook
56006_1.00

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