AMD Vega 10 User Manual

Table 3–25 Rom-based Straps
Strap Name Description BIOS
Address
Default
BIOS
Setting
STRAP_BIF_STRAP_64BAR_DIS_DEV0_F0 Enable 64-bit BAR for
Function 0.
Affects bit 2 of
BLOCK_MEM_TYPE for
each BAR register in the
PCI configuration space.
0×A8
Bit 26
0
STRAP_BIF_STRAP_SUBSYS_VEN_ID_DEV0_F0 Subsystem Vendor ID
(SSVID) in the PCI
configuration space.
If the VBIOS ROM is not
used, then the SBIOS is
permitted to overwrite this
register for each PCI
function on the device
before the enumeration
cycle is initiated, otherwise
the default value is used.
0×B8 Bit
29
to
0×BC Bit
12
0×1002
STRAP_BIF_STRAP_SUBSYS_ID_DEV0_F0 Subsystem ID (SSID) for the
PCI configuration space for
Function 0.
If enabled, the SSID for the
secondary display function
(F1) is the set to the same
value as the primary display
function (F0) with bit 0
inverted.
0×B0
Bits 4 to
19
STRAP_BIF_STRAP_MEM_AP_SIZE_DEV0_F0 Size of the primary memory
apertures claimed in the
PCI configuration space.
000 = 256 MB
001 = 512 MB
010 = 1 GB
011 = 2 GB
100 = 4 GB
101 = 8 GB
110 = 16 GB
111 = 32 GB
It is a shared pin strap with
ROM_CONFIG[2:0] if
BIOS_ROM_EN is set to 0.
0×C0
Bits 7 to
9
Depends on
board
configuration.
STRAP_BIF_STRAP_FUNC_EN_DEV0_F1 Multi-function device
select.
Affects bit 7 of the Header
register in PCI
configuration space.
PCI configuration setting:
0 - Audio function not
present.
1 - Audio function present.
Boards with a ROM will
require both the ROM and
the specific pin straps to be
0×B8
Bit 12
Depends on
board
configuration.
Signal Descriptions 41
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"Vega 10" Databook
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AMD Vega 10 Specifications

General

Process Size	14 nm
Transistor Count	12.5 billion
Memory Type	HBM2
GPU	Vega 10
Stream Processors	4096
Texture Units	256
ROPs	64
Memory Size	8 GB
Die Size	486 mm²
Memory Bandwidth	483.8 GB/s
Compute Units	64
FP32 (float) Performance	12.66 TFLOPS
Memory Bus	2048-bit