4.2 Initialization Sequence and Timing
4.2.1 Initialization Sequence and Timing
1. Chip reset (PERSTB) is asserted, and PCIE_REFCLK starts running.
2. All GPIOs go to a tristate (input) mode at RESETB. Some GPIOs have internal
pull-down (PD) or pull-up (PU) resistors—see descriptions of pin-based straps.
3. External pin straps are driving their values onto the GPU pins.
4. Chip reset (PERSTB) is deasserted.
5. External pin-strap values are latched internally.
6. In parallel:
a. eFuse state machine begins to read "eFuse straps."
b. If a ROM exists (and is programmed), a request is sent to the ROM
controller to read the "ROM straps."
7. eFuse and ROM straps are "forwarded" to PHY.
8. In parallel:
a. If GPU memory repair is required, then memory repair starts.
b. eFuse and ROM straps are "forwarded" to other blocks in the GPU.
9. Wait for memory repair to complete. De-assert a hard reset to all the blocks
including BIF. Enable PCIe® PHY impedance calibration. After polling for the
PHY impedance calibration, distribute the remaining fuses and poll for BIF to
complete its reset sequence.
10. The GPU begins link training according to the PCIe specification.
After link training and the reset sequence are complete, the system is ready for
the first transaction, such as a configuration space request.
The following figure and table provide an outline of the "Vega 10" reset sequence.
Timing Specifications 47
© 2017 Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
"Vega 10" Databook
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