Table 3–6 Integrated HDMI™/TMDS Interface
Pin Name Type Description
TX[5:3]P/M_DPA[0:2]P/N
TX[2:0]P/M_DPB[0:2]P/N
TX[5:3]P/M_DPC[0:2]P/N
TX[2:0]P/M_DPD[0:2]P/N
TX[5:3]P/M_DPE[0:2]P/N
TX[2:0]P/M_DPF[0:2]P/N
O TMDS data pairs (+/-).
Transmitting at a bit rate of 10× pixel clock, up to 594-MHz
pixel clock.
A 100-nF capacitor is required on each differential signal
placed near the connector.
A 500-Ω resistor to ground is required on each differential-
signal line. One FET is needed to disconnect the path from
the 500-Ω resistors to ground when the system is off and the
panel is on.
TXCAP/M_DPA3P/N
TXCBP/M_DPB3P/N
TXCCP/M_DPC3P/N
TXCDP/M_DPD3P/N
TXCEP/M_DPE3P/N
TXCFP/M_DPF3P/N
O TMDS clock channels (+/-).
A 100-nF capacitor is required on each differential signal
placed near the connector.
A 500-Ω resistor to ground is required on each differential-
signal line. One FET is needed to disconnect the path from
the 500-Ω resistors to ground when the system is off and the
panel is on.
DDC[2:1]CLK
DDC[2:1]DATA
DDCAUX[6:3]N
DDCAUX[6:3]P
I/O Differential signals for HDMI/TMDS DDC. For more details,
see Table 3–14 (p. 31).
NOT 5-V tolerant.
AUX_ZVSS
A Analog calibration.
Connect to VSS through a 150-Ω (1%) resistor.
DP_ZVDD_08
A Analog calibration.
Connect to VDD_080 through a 200-Ω (1%) resistor.
DP_ZVSS
A Analog calibration.
Connect to GND through a 200-Ω (1%) resistor.
Note: For native dual-link DVI support, contact AMD.
3.6 DisplayPort
Note: If this interface is not used, all signal outputs can be unconnected. AUX_ZVSS,
DP_ZVDD_08, and DP_ZVSS should always be connected.
"Vega 10" supports six DisplayPort links.
The GPU and DisplayPort connector are on the same PCB with a maximum trace
length of 127 mm or 5 inches.
Please refer to the DisplayPort Standard Version 1.4 for additional details.
24 Signal Descriptions
"Vega 10" Databook
56006_1.00
© 2017 Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
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