AMD Vega 10 - JTAG Timing Characteristics

8.4 JTAG Timing Characteristics
Table 8–2 JTAG Timing Characteristics
Symbol Description Min Max
f
cyc
Frequency of operation. 0.001 MHz 10 MHz
t
cyc
TCK cycle period. 0.10 µs 1000 µs
t
bsst
Input data setup time to TCK rise. 15 ns
t
bsht
Input data hold time to TCK rise. 20 ns
t
bsdv
TCK low to output data valid. 0.00 µs 0.05 µs
t
tcst
TDI, TMS setup time to TCK rise. 2.5 ns
t
tcht
TDI, TMS hold time to TCK rise. 3.0 ns
t
tcdv
TCK low to TDO data valid. 0.0 µs 0.05 µs
Figure 8–1 Timing of the Boundary Scan Signals with Respect to TCK
Figure 8–2 Timing of the TAP Ports (TDI, TMS, and TDO) with Respect to TCK
78 Boundary Scan Specification
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