3.4 Display Configuration Overview
"Vega 10" has six display links, A to F.
Table 3–5 Display Configuration Overview for Links A, B, C, D, E, and F
Pin Name Possible Display Configurations
TX[5:3]P/M_DPA[0:2]P/N
TXCAP/M_DPA3P/N
Single-link
DisplayPort/
TMDS
DisplayPort can be connected to any of links A, B,
C, D, E, or F. The six links are independent and can
be simultaneously active.
HDMI or single-link DVI can be connected to any of
the links (A, B, C, D, E, or F).
For native dual-link DVI support, contact AMD.
TX[2:0]P/M_DPB[0:2]P/N
TXCBP/M_DPB3P/N
Single-link
DisplayPort/
TMDS
TX[5:3]P/M_DPC[0:2]P/N
TXCCP/M_DPC3P/N
Single-link
DisplayPort/
TMDS
TX[2:0]P/M_DPD[0:2]P/N
TXCDP/M_DPD3P/N
Single-link
DisplayPort/
TMDS
TX[5:3]P/M_DPE[0:2]P/N
TXCEP/M_DPE3P/N
Single-link
DisplayPort/
TMDS
TX[2:0]P/M_DPF[0:2]P/N
TXCFP/M_DPF3P/N
Single-link
DisplayPort/
TMDS
3.5 Integrated HDMI™/TMDS Interface
"Vega 10" has six display links, A to F.
Note:
• The maximum pixel clock rate is 594 MHz on direct connectors. The GPU and
HDMI™ connector are on the same PCB with a maximum trace length of 127
mm or 5 inches, and may be affected by TMDS signals layout and trace lengths.
• For unused interfaces, all signal outputs can be unconnected. AUX_ZVSS,
DP_ZVDD_08, and DP_ZVSS should always be connected.
Please refer to the Digital Visual Interface (DVI) 1.0 Specification and the High-
Definition Multimedia Interface (HDMI) Specification for additional details.
Signal Descriptions 23
© 2017 Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
"Vega 10" Databook
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