AMD Vega 10 User Manual

2.6 PCI Express® Bus Support Features
• Compliant with the PCI Express® Base Specification Revision 3.0, up to 8.0 GT/
s.
• Supports ×1, ×2, ×4, ×8, and ×16 lane widths.
• Supports 2.5 GT/s, 5.0 GT/s, and 8.0 GT/s link-data rates.
• Supports ×16 lane reversal where the receivers on lanes 0 to 15 on the graphics
endpoint are mapped to the transmitters on lanes 15 down to 0 on the root
complex.
• Supports ×16 lane reversal where the transmitters on lanes 0 to 15 on the
graphics endpoint are mapped to the receivers on lanes 15 down to 0 on the
root complex (requires corresponding support on the root complex).
• Supports full-swing and low-swing transmitter output levels.
2.7 Power Management Features
• Intelligent monitoring and control of power, current and temperature through
AMD PowerTune technology:
• Includes temperature monitoring and control of the GPU as well as HBM
memory.
• Improved response to track smoothly to the defined thermal and power
limits.
•
Support for I
2
C-based monitoring of voltage regulator temperature.
• Dynamic Power Management (DPM) defines multiple power levels for different
clock and voltage domains to achieve best overall performance and idle power:
• DPM includes intelligent firmware control to operate the different
domains at the ideal operating point based on activity running in the
system.
• "Vega 10" supports DPM on most clock domains including engine,
memory, data fabric, multimedia, etc.
• Improved DPM response for performance and/or performance per watt
optimization based on the type of workload.
• Adaptive Voltage and Frequency Scaling (AVFS) on graphics engine clock to
optimize the V-F curve that each part operates on.
• Adaptive clock generator (also know as “Clock Stretcher”) on graphics engine
clock to stretch the clock dynamically during didt/droop events. This helps
reduce droop guardbands and improves performance per watt.
• Improved clock gating for better power and performance per watt efficiency on
different SOC blocks.
• Electrical design current (EDC) mitigation and control using the on-die EDC
controller.
• Dram self-refresh and display stutter.
• Data fabric operates at low power states when idle.
Functional Overview 15
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"Vega 10" Databook
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AMD Vega 10 Specifications

General

Process Size	14 nm
Transistor Count	12.5 billion
Memory Type	HBM2
GPU	Vega 10
Stream Processors	4096
Texture Units	256
ROPs	64
Memory Size	8 GB
Die Size	486 mm²
Memory Bandwidth	483.8 GB/s
Compute Units	64
FP32 (float) Performance	12.66 TFLOPS
Memory Bus	2048-bit