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AMD Vega 10 - Configuration Straps; Pin-Based Straps; Table 3-23 Other Signals

AMD Vega 10
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Pin Name Voltage Description
VDDAN_Q_EFUSE 1.8 V Can be merged and share the same regulator with VDD_18.
VDDCR_SOC 0.8 V - 1.25
V
Dedicated core power; provides power to the internal logic.
SVI2 regulator set voltage.
FB_VDDCR_SOC - Provides VDDCR_SOC feedback path to the regulator.
If unused, connect to a test point or leave unconnected.
VDDAN_33 3.3 V I/O power for 3.3-V pins, such as GPIOs and AUX.
VSS 0 V Ground.
FB_VSS_A FB of VSS Provides VSS_A feedback path to the regulator.
Route differentially with FB_VDDCR_SOC to the core regulator.
If unused, connect to a test point or leave unconnected.
FB_VSS_B FB of VSS Provides VSS_B feedback path to the regulator.
Route differentially with FB_VDDIO_MEM_HBM/
FB_VDDIO_MEM_GPU/FB_VDDCR_HBM to the memory
regulator.
If unused, connect to a test point or leave unconnected.
Table 3–23 Other Signals
Pin Name Type Description
TEST_PG
TEST_PG_BACO
I/O
(VDDAN_18)
TEST_PG and TEST_PG_BACO must be connected to the 1.8-V power
rail through pull-up resistors for normal operation.
TS_A
I/O
(VDD_18)
Not connected on the PCB. Provide test pad.
GENERICA/B
I/O
(VDDAN_33)
General purpose I/O or open-drain output.
MACO_EN
I/O Reserved for future purposes.
3.21 Configuration Straps
3.21.1 Pin-based Straps
"Vega 10" uses pin straps (i.e., one pin for one strap).
Some of the straps are on 3.3-V GPIOs while others are on dedicated 1.8-V strap pins.
Each strap pin has either an internal pull-down resistor which provides a default value
of 0, or an internal pull-up resistor which provides a default value of 1, at power up.
For each strap that defaults to 0 by the GPU, provide a pull-up resistor option (to 3.3-
V or 1.8-V depending on if the pin is 3.3 V to 1.8 V) on the PCB. For each strap that
defaults to 1 by the GPU, provide a pull-down resistor option to GND on the PCB.
Any external circuit using these pins must not conflict with the logic level required
by the strap after power up until PCIe reset gets de-asserted.
Signal Descriptions 37
© 2017 Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
"Vega 10" Databook
56006_1.00

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