AMD Vega 10 User Manual

4.4 LCD Panel Power-up/down Timing (eDP Interface)
Figure 4–5 eDP Panel Power-up/down Timing
Note: The Aux CH response from sink is dependent on the application of LCDVCC.
Table 4–3 Registers for Setting Backlight PWM Parameters
Parameter Description Time (ms)
T1+T2
Power rail rise time from 10% to 90% and delay from LCDVDCC to
black video generation
Hardware controlled,
up to 210 ms
T3
Delay from LCDVCC active to HPD high and Aux Software controlled
T4
Delay from HPD high to link training initialization Software controlled
T8
Delay from “Valid Video Data” to ENA_BL/VARY_BL active Software controlled
T9
Delay from ENA_BL/VARY_BL inactive to the end of “Valid Video
Data”
Software controlled
T10
Delay from “Source Main-Link Data” off to LCDVCC Off Software controlled
T11
Power rail fall time from 90% to 10%
Hardware controlled,
up to 10 ms
T12
Minimum panel off duration (off time is ≥ T12) Software controlled
Timing Specifications 51
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"Vega 10" Databook
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AMD Vega 10 Specifications

General

Process Size	14 nm
Transistor Count	12.5 billion
Memory Type	HBM2
GPU	Vega 10
Stream Processors	4096
Texture Units	256
ROPs	64
Memory Size	8 GB
Die Size	486 mm²
Memory Bandwidth	483.8 GB/s
Compute Units	64
FP32 (float) Performance	12.66 TFLOPS
Memory Bus	2048-bit