AMD Vega 10 - Standard Boot-Up Sequence; Figure 4-3 Reset Sequence; Table 4-1 Power-On Reset Sequence Timing Parameters

Figure 4–3 Reset Sequence
Table 4–1 Power-on Reset Sequence Timing Parameters
Parameter Description Minimum Time Maximum Time
T
RAMP-UP
Power rail ramp-up time
0 ms 20 ms
T
PVPERL
All GPU power rails stable to PERSTB inactive
100 ms Not limited
T
PERST-CLK
PCIE_REFCLK stable before PERSTB inactive
100 µs Not limited
T
RST-SEQ-A
The time required by the GPU to complete its internal
reset sequence, and become ready for PCI
configuration space access
N/A 100 ms
T
RST-SEQ-B
The time the system software must wait after de-
assertion of PERSTB before accessing the GPU's PCI
configuration space
100 ms Not limited
T
RAMP-DOWN
Power rail ramp-down time
0 ms 20 ms
T
FAIL
Power level invalid to PERSTB active
No requirements No requirements
T
PERST
PERSTB active time
100 µs Not limited
4.2.2 Standard Boot-up Sequence
1. PERSTB (fundamental reset) is asserted to the device.
2. Select internal-strap values are determined by the configuration of pin straps
on a subset of GPIOs on the board.
48 Timing Specifications
"Vega 10" Databook
56006_1.00
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AMD Confidential - Do not duplicate.