Pin Name Type PD/PU Description
GPIO_12 I/O
3.3V
(VDDAN_33)
PD-reset General purpose I/O and pin strap.
See Table 3–24 (p. 38) for pin strap definition.
GPIO_13 I/O
3.3V
(VDDAN_33)
PD-reset General purpose I/O and pin strap.
See Table 3–24 (p. 38) for pin strap definition.
GPIO_14 I/O
3.3V
(VDDAN_33)
PD-reset General purpose I/O.
GPIO_15 I/O
3.3V
(VDDAN_33)
PD-reset General purpose I/O and pin strap.
See Table 3–24 (p. 38) for pin strap definition.
GPIO_16 I/O
3.3V
(VDDAN_33)
PD-reset General purpose I/O and pin strap.
See Table 3–24 (p. 38) for pin strap definition.
GPIO_17 I/O
3.3V
(VDDAN_33)
PD-reset General purpose I/O and pin strap.
See Table 3–24 (p. 38) for pin strap definition.
GPIO_18 I/O
3.3V
(VDDAN_33)
PD-reset General purpose I/O and pin strap.
Can be unconnected if not used.
See Table 3–24 (p. 38) for pin strap definition
GPIO_19 I/O
3.3V
(VDDAN_33)
PD-reset General purpose I/O and pin strap.
See Table 3–24 (p. 38) for pin strap definition.
GPIO_20 I/O
3.3V
(VDDAN_33)
PD-reset Do not connect on the PCB. Provide a test pad.
Note:
1. During ramp-up of the VDDAN_33 power rail, all GPIOs are undefined and a voltage bump may
appear momentarily (less than 200 mV).
2. Internal PU or PD is effective after VDDCR_SOC is at ready state. Before VDDCR_SOC is ready, the
GPIOs are of Hi-Z state.
3. All GPIOs are configured as input by default after VDDCR_SOC is at ready state. GPIOs can be
programmed as output by the video BIOS or driver.
4. For GPIOs that serve as pin straps, any external circuits using them must not conflict with the logic
level required by the strap after power up until PCIe reset gets de-asserted.
5. See Configuration Straps (p. 37) for more information on pin strap configurations.
28 Signal Descriptions
"Vega 10" Databook
56006_1.00
© 2017 Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
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