AMD Vega 10 - Page 56

d. The SMBus slave acknowledges the master.
e. The SMBus master issues an 8-bit CMD_LD_ADDR command to the slave.
f. The SMBus slave acknowledges the master.
g. The SMBus master sends a byte count (always 4).
h. The SMBus slave acknowledges the master.
i. The SMBus master issues a 4-bit byte enable with a 4-bit zero padding.
j. The SMBus slave acknowledges the master.
k. The SMBus master sends SMB_ADDR[25:18] to the slave.
l. The SMBus slave acknowledges the master.
m. The SMBus master sends SMB_ADDR[17:10] to the slave.
n. The SMBus slave acknowledges the master.
o. The SMBus master sends SMB_ADDR[9:2] to the slave.
p. The SMBus slave acknowledges the master.
q. The SMBus master sends a STOP bit to the slave.
2. Issuing a Write Data Command to the SMB_WR_DATA register:
a. The SMBus master issues a START bit to the slave.
b. The SMBus master issues a 7-bit slave address to the slave.
c. The SMBus master issues a write bit to the slave.
d. The SMBus slave acknowledges the master.
e. The SMBus master issues an 8-bit CMD_WR_DATA command to the slave.
f. The SMBus slave acknowledges the master.
g. The SMBus master sends a byte count (always 4).
h. The SMBus slave acknowledges the master.
i. The SMBus master sends SMB_WR_DATA[31:24] to the slave.
j. The SMBus slave acknowledges the master.
k. The SMBus master sends SMB_WR_DATA[23:16] to the slave.
l. The SMBus slave acknowledges the master.
m. The SMBus master sends SMB_WR_DATA[15:8] to the slave.
n. The SMBus slave acknowledges the master.
o. The SMBus master sends SMB_WR_DATA[7:0] to the slave.
p. The SMBus slave acknowledges the master.
q. The SMBus master sends a STOP bit to the slave.
44 Timing Specifications
"Vega 10" Databook
56006_1.00
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