AMD Vega 10 - Page 66

Register Field Description
[BL_PWM_REF_DIV] ) cycles in
each backlight period. The
BL_PWM_PERIOD_BITCNT
register field represents how
many LSBs of this register field,
from 1 to 16, are actually used as
the backlight period value.
DISPOUT.BL_PWM_CNTL.BL_ACTIVE_INT_FRAC_CNT
This 16-bit value specifies the
backlight active duty cycle, in
units of divided reference clock
cycles (similar to the backlight
period). This value consists of
both an integer component and
potentially a fractional
component of the active duty
cycle.
The BL_PWM_PERIOD_BITCNT
MSBs of this register field
represent the integer component
of the active duty cycle. This
applies regardless of whether
fractional active duty mode
(BL_PWM_FRACTIONAL_EN) is
enabled or disabled.
The valid range for the integer
component of the active duty
cycle, contained in the
(BL_PWM_PERIOD_BITCNT)
MSBs of this register, is from 0 up
to the BL_PWM_PERIOD value
(contained in the
(BL_PWM_PERIOD_BITCNT)
LSBs of the BL_PWM_PERIOD
register value).
When fractional active duty cycle
mode is enabled, the (16 -
BL_PWM_PERIOD_CNT) LSBs of
this register field represent the
fractional component of the active
duty cycle.
54 Timing Specifications
"Vega 10" Databook
56006_1.00
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AMD Confidential - Do not duplicate.