ARM ARM7TDMI Hardware Reference Guide

Open Access
A-21
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
Board Schematics
A.20 Master Header Connecters and Level Converters
Date: February 26, 1996 Sheet
Size Document Number
B ARM EOI-0011B (MASTE
R
Title
ARM Master Header and Level
CB1 4JN
Cambridge
Cherry Hinton
Fulbourn Road
(c) ADVANCED RISC MACHI
N
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
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21
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23
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25
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27
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29
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31
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33
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35
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37
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39
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41
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43
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49
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51
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53
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55
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59
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2
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42
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44
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46
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48
+
50
+
52
+
54
+
56
+
58
+
60
PL9
CON60AP
GND
GND
CPB
CPA
GND
GND
COMMTX
TRAN0
nCPI
ERROR
MCLK
nIRQ
COM
M
TRA
N
WAI
T
nFI
Q
LAS
T
RES1
RES0
RES2
BEN
D
nIC
E
ISYNC
HEADER CONNECTORS
(TDO)
(TMS)
(TDI)
(TCK)
+
1
+
3
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5
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7
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9
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11
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13
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15
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17
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19
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21
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25
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27
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29
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31
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35
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51
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53
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55
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57
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59
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6
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8
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10
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12
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14
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16
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18
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20
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22
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24
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26
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30
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32
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34
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36
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40
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42
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44
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46
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48
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50
+
52
+
54
+
56
+
58
+
60
PL8
CON60AP
D0
D2
D3
D11
D12
D15
D17
D18
D20
D21
D5
D6
D8
D9
D14
GND
GND
GND
EXTERN1
EXTERN0
REQARM
GNTARM
REQ001
GNT001
nTRST
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
+
21
+
23
+
25
+
27
+
29
+
31
+
33
+
35
+
37
+
39
+
41
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43
+
45
+
47
+
49
+
51
+
53
+
55
+
57
+
59
+
2
+
4
+
6
+
8
+
10
+
12
+
14
+
16
+
18
+
20
+
22
+
24
+
26
+
28
+
30
+
32
+
34
+
36
+
38
+
40
+
42
+
44
+
46
+
48
+
50
+
52
+
54
+
56
+
58
+
60
PL6
CON60AP
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
+
21
+
23
+
25
+
27
+
29
+
31
+
33
+
35
+
37
+
39
+
41
+
43
+
45
+
47
+
49
+
51
+
53
+
55
+
57
+
59
+
2
+
4
+
6
+
8
+
10
+
12
+
14
+
16
+
18
+
20
+
22
+
24
+
26
+
28
+
30
+
32
+
34
+
36
+
38
+
40
+
42
+
44
+
46
+
48
+
50
+
52
+
54
+
56
+
58
+
60
PL7
CON60AP
A0
A2
A3
A5
A6
A8
A9
A11
A12
A14
A15
A17
A18
A20
A21
A23
A24
A26
A27
GND
GND
D1
GND
D10
GND
D13
D16
GND
D19
D4
D7
B_WRITE
B_TRAN[1..0]
B_LOCK
B_SIZE[1..0]
B_PROT[1..0]
A_GNTARM
A_GNT001
B_A[31..0]
B_D[31..0]
B_RES[2..0]
B_CLK6
A_GNTARM
B_A[31..0]
B_D[31..0]
B_WRITE
B_SIZE[1..0]
B_TRAN[1..0]
B_RES[2..0]
B_PROT[1..0]
B_LOCK
GND
A1
A4
GND
A7
A10
GND
A13
A16
GND
A19
A22
GND
A25
A_GNT001
B_CLK6
OE
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U44
QS3245
B_WAIT
B_LAST
B_ERROR
ARMnFIQ
ARMnIRQ
BIGEND
nJTRST
ARMnFIQ
ARMnIRQ
B_WAIT
B_LAST
B_ERROR
A28
GND
A31
SIZE1
GND
PROT0
GNDA0
A1
A2
A3
A4
A5
A6
A7
B_A0
B_A1
B_A2
B_A3
B_A4
B_A5
B_A6
BIGEND
VLL1 VLL1
nJTRST
OE
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U42
QS3245
A29
A30
WRITE
SIZE0
PROT1
LOCK
VDD
D22
GND
D25
GND
D28
D31
GNDA16
A17
A18
A19
A20
A21
A22
A23
B_A16
B_A17
B_A18
B_A19
B_A20
B_A21
B_A22
D0
D1
D2
D3
D4
D5
D6
D7
VLL2 VLL2 VLL3
OE
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U46
QS3245
OE
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U48
QS3245
D23
D24
VDD
D26
D27
D29
D30
VDD
GND
GND D16
D17
D18
D19
D20
D21
D22
D23
B_D0
B_D1
B_D2
B_D3
B_D4
B_D5
B_D6
VLL3 VLL4
MONI
VDD
ISY
N
GND
VCC
GND
B_D16
B_D17
B_D18
B_D19
B_D21
B_D22
B_D20
CPA
nCPI
CPB
EXT
E
EXT
E
VLL4
OE
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U53
QS3245
1
1
1
A_REQAR
M
A_REQ00
1
GND
B_D23
B_D24
B_D25
B_D26
B_D27
B_D28
B_D29
B_D30
B_D31
ARMCOMM
T
ARMCOMM
R
GND
nSYSRST
nSYSRST
VLL4
VLL8
nTRST
OE
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U47
QS3245
OE
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U49
QS3245
OE
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U52
QS3245
1
V191
1
V192
1
V193
1
V194
GND
GND
GND
D24
D25
D26
D27
D28
D29
D30
D31
B_D7
B_D8
B_D9
B_D10
B_D11
B_D12
B_D13
B_D14
B_D15
GND
B_RES0
B_RES1
B_RES2
B_WAIT
B_ERROR
nICERST
VLL3 VLL4
VLL7
VLL8
nJTRST
OE
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U43
QS3245
OE
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U51
QS3245
GND
GND
GNDA24
A25
A26
A27
A28
A29
A30
A31
B_A23
B_A24
B_A25
B_A26
B_A27
B_A28
B_A29
B_A30
B_A31
GND
GND
D8
D9
D10
D11
D12
D13
D14
D15
GNDREQARM
GNTARM
REQ001
GNT001
A_REQARM
A_GNTARM
A_REQ001
A_GNT001nFIQ
nIRQ ARMnFIQ
RES0
RES1
RES2
WAIT
ERROR
LAST
VLL2 VLL2 VLL3
VLL6 VLL6 VLL7
OE
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U45
QS3245
OE
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U50
QS3245
GND
GND
GNDA8
A9
A10
A11
A12
A13
A14
A15
B_A7
B_A8
B_A9
B_A10
B_A11
B_A12
B_A13
B_A14
B_A15
GNDSIZE0
SIZE1
PROT0
PROT1
WRITE
LOCK
B_SIZE0
B_SIZE1
B_PROT0
B_PROT1
B_WRITE
VLL1 VLL1
VLL5 VLL5
C96
10n
R184
2K2
D14
1N4001
C97
10n
R185
2K2
D15
1N4001
C98
10n
D16
1N4001
GND
B_LOCKTRAN0
TRAN1 B_TRAN0
B_TRAN1
VLL1 VLL2 VLL3
VCC VCC VCC
GND GND
LEVEL SHIFTER INDIVIDUAL POWER SUPPLIES
LEVEL SHIFTERS 5V -> 4.3V
R186
2K2
C99
10n
R187
2K2
D17
1N4001
C100
10n
R188
2K2
D18
1N4001
C101
10n
D19
1N4001
GND GND
COMMRX
COMMTX ARMCOMMRX
ARMCOMMTX
ARMnIRQ MCLK
BEND
VLL4 VLL5 VLL6
VCC VCC VCC
GND GND GND
R189
2K2
C102
10n
R190
2K2
D20
1N4001
C103
10n
R191
2K2
D21
1N4001
1
V195
1
V196
B_LAST
BIGEND
GND
B_CLK6
VLL7 VLL8
VCC VCC
GND GND GND
SPARE LEVEL SHIFTERS
1
1
1
h
rg.
b
oo
k
P
age
21
W
e
d
nes
d
ay,
J
u
l
y
22
,
1998
9
:
18
AM

ARM ARM7TDMI Specifications

General

Brand	ARM
Model	ARM7TDMI
Category	Computer Hardware
Language	English