ARM ARM7TDMI Hardware Reference Guide

Open Access
A-11
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
Board Schematics
A.10 APB and NISA Bridge
Date: February 26, 1996 Sheet
Size Document Number
B EOI-011B (ASBNISA.
S
Title
APB and NISA Brid
g
CB1 4JN
CAMBRIDGE
CHERRY HINTON
FULBOURN ROAD
(C) ADVANCED RISC MAC
APB EX
P
APBEXP
P_WRI
T
P_STB
P_A[3
1
P_D[3
1
P_SEL
E
B_RES
P_SEL
I
P_SEL
C
P_SEL
R
nB_CL
K
B_CLK
1
nINTA
P
nFIQS
R
P_A[31..0]
P_D[31..0]
P_WRITE
P_STB
P_SELEX
B_RES[2..0]
INTPCA
INTPCB
INTSPA
INTSPB
nINTPP
P_SELIC
P_SELCT
P_SELRC
ARMCOMMTX
ARMCOMMRX
APB SLAVES
APBSLAVE.SCH
P_WRITE
P_STB
P_SELIC
P_SELCT
P_SELRC
P_A[31..0]
P_D[31..0]
B_RES[2..0]
P_SELEX
nINTPP
INTPCB
INTSPA
INTSPB
INTPCA
ARMCOMMRX
ARMCOMMTX
ARMnFIQ
STANDBY
REMAP
ARMnIRQ
B_CLK0
nINTAPB[2..0]
nINTASB[1..0]
nFIQSRC
P_A[31..0]
P_D[31..0]
P_WRITE
P_STB
P_SELIC
P_SELCT
P_SELRC
P_SELEX
B_RES[2..0]
APB BUFFERS
APBBUF.SCH
nB_DEN
nB_DLEN
nP_DEN
nP_DLEN
P_D[31..0]
B_A[31..0]
B_D[31..0]
nP_ALEN
P_A[31..26]
P_A[22..9]
P_A[1..0]
P_A[31..26]
P_A[1..0]
P_A[22..9]
B_A[31..0]
B_D[31..0]
B_WRITE
B_SIZE[1..0]
B_RES[2..0]
D_SELNISA
D_SELAPB
B_CLK[2..0]
COMMCLK
B_A[31..0]
B_D[31..0]
B_WRITE
B_SIZE[1..0]
B_RES[2..0]
B_CLK[2..0]
D_SELAPB
D_SELNISA
nB_DEN
nB_DLEN
nP_DEN
nP_DLEN
nP_ALEN
COMMCLK
SPARE I/O
1
V77
B_WAIT
nFIQSRC
nINTASB[1..0]
ARMCOMMRX
ARMCOMMTX
nB_CLK[2..1]
ARMnFIQ
ARMnIRQ
STANDBY
NISARST
NISACLK0
B_WAIT
nFIQSRC
nINTASB[1..0]
ARMCOMMRX
ARMCOMMTX
nB_CLK[2..1]
ARMnFIQ
ARMnIRQ
STANDBY
NISARST
NISACLK0
APB AND NISA BRIDGE
MONITOR POINTS
1
V69
1
V70
1
V71
1
V72
1
V73
1
V74
1
V81
V
C
C
G
N
D
V
C
C
G
N
D
B
_
A
8
Q
0
Q
2
Q
3
Q
4
S
S
T
A
T
E
0
B
_
W
R
I
T
E
B
_
W
A
I
T
n
I
O
R
n
I
O
W
n
M
E
M
R
n
M
E
M
W
n
S
B
H
E
B
A
L
E
S
A
P
B
A
C
K
P
C
C
L
K
NISA BUS PERIPHERALS
NISABUS.SCH
nCSA
nCSB
nCSP
BALE
RDY
INTPCA
INTPCB
INTSPA
INTSPB
nINTPP
nSBHE
nMEMR
nMEMW
nIOR
nIOW
nRESET
NISARST
P_D[15..0]
P_A[24..0]
nM16
nIO16
nZWS
COMMCLK
PCCLK
P_A[24..0]
P_D[15..0]
nCSA
B_CLK0
ARMnFIQ
ARMnIRQ
STANDBY
REMAP
nINTAPB[2..0]
nFIQSRC
nINTASB[1..0]
INTPCA
INTPCB
INTSPA
nB_CLK1
B_CLK1
INTSPB
nINTPP
nCSB
nCSP
BALE
nM16
nIO16
nZWS
nSBHE
nMEMR
nMEMW
nIOR
nIOW
COMMCLK
GND
VCC
B_CLK2
nB_CLK2
P_A23
B_A5
B_A23
B_A24
B_A25
B_RES0
B_RES1
GND
STROBE2
nP_DLEN
nP_ALEN
nB_DEN
MONITOR POINTS
1
V75
1
V78
1
V79
1
V80
IO8
12
IO9
13
IO10
14
IO11
15
IO12
16
IO13
17
IO14
18
IO15
19
CLK0/I0
20
VCC
21
GND
22
CLK1/I1
23
IO16
24
IO17
25
IO18
26
IO19
27
IO20
28
IO21
29
IO22
30
IO23
31
GND
32
I
O
2
4
3
3
I
O
2
5
3
4
I
O
2
6
3
5
I
O
2
7
3
6
I
O
2
8
3
7
I
O
2
9
3
8
I
O
3
0
3
9
I
O
3
1
4
0
I
2
4
1
V
C
C
4
2
G
N
D
4
3
V
C
C
4
4
I
O
3
2
4
5
I
O
3
3
4
6
I
O
3
4
4
7
I
O
3
5
4
8
I
O
3
6
4
9
I
O
3
7
5
0
I
O
3
8
5
1
I
O
3
9
5
2
G
N
D
5
3
IO40
54
IO41
55
IO42
56
IO43
57
IO44
58
IO45
59
IO46
60
IO47
61
CLK2/I3
62
VCC
63
GND
64
CLK3/I4
65
IO48
66
IO49
67
IO50
68
IO51
69
IO52
70
IO53
71
IO54
72
IO55
73
GND
74
I
O
5
6
7
5
I
O
5
7
7
6
I
O
5
8
7
7
I
O
5
9
7
8
I
O
6
0
7
9
I
O
6
1
8
0
I
O
6
2
8
1
I
O
6
3
8
2
I
5
8
3
V
C
C
8
4
G
N
D
1
V
C
C
2
I
O
0
3
I
O
1
4
I
O
2
5
I
O
3
6
I
O
4
7
I
O
5
8
I
O
6
9
I
O
7
1
0
G
N
D
1
1
U20
MACH231-7
REMAP
REMAP
SNM16
P_SELEX
P_SELCT
P_SELRC
SNZWS
SRDY
SNIO16
P_SELIC
D_SELNISA
P_A5
P_A6
B_A7
P_STB
VCC
GND
NISACLK0
SELECT STROBE WIDTH
OUT - 2 cycle (default)
IN - 1 cycle
MONITOR POINT
1
2
LK7
LINK
R109
10K
1
V76
B_A6
GND
P_A0
B_SIZE0
B_SIZE1
STROBE2
VCC
GND
DECOUPLING CAPACITORS
C53
10u
P
_
A
2
P
_
A
3
P
_
A
4
P
_
A
7
P
_
A
8
P_A24
P_A25
B
_
A
2
B
_
A
3
B
_
A
4
nM16
nIO16
RDY
n
P
_
D
E
N
G
N
D
V
C
C
G
N
D
V
C
C
n
B
_
D
L
E
N
P
_
W
R
I
T
E
D
_
S
E
L
A
P
B
n
Z
W
S
n
C
S
A
n
C
S
B
n
C
S
P
S
D
S
E
L
N
I
S
A
C54
100n
C55
100n
C56
100n
C57
100n
B_RES0
RDY
VCC
GND
NISARST
PCCLK
VCC
GND
h
rg.
b
oo
k
P
age
11
W
e
d
nes
d
ay,
J
u
l
y
22
,
1998
9
:
18
AM

ARM ARM7TDMI Specifications

General

Data Width	32-bit
Cores	1
MIPS per MHz	0.9
On-chip Debug	Yes
Instruction Set	ARM
Pipeline Stages	3
Operating Voltage	Implementation dependent
Manufacturing Process	Implementation dependent