ARM ARM7TDMI Hardware Reference Guide

Open Access
A-16
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
Board Schematics
A.15 APB Slaves
Date: February 26, 1996 Sheet
Size Document Number
B ARM EOI-0011B (APBSLA
V
Title
APB Slaves
CB1 4JN
Cambridge
Cherry Hinton
Fulbourn Road
(c) ADVANCED RISC MACHI
N
R161
1K
ARMnF
ARMnFIQ
VCC
SPARE I/O
1
V96
1
V97
VCC
P
_
A
1
6
P
_
A
1
7
P
_
A
1
8
P
_
A
1
9
P
_
A
2
0
P
_
A
2
1
P
_
A
2
2
P
_
A
2
3
CCLK
G
N
D
G
N
D
GND
1
A16+
2
A17+
3
P4
4
P5
5
P6
6
P7
7
NC
8
NC
9
GND
10
P11
11
P12
12
P13
13
P14
14
P15
15
P16
16
P17
17
P18
18
GND
19
VCC
20
P21
21
P22
22
P23
23
P24
24
P25
25
P26
26
P27
27
P28
28
GND
29
NC
30
NC
31
P32
32
P33
33
P34
34
P35
35
P36
36
P37
37
M1
38
GND
39
M0
40
V
C
C
4
1
M
2
4
2
P
4
3
4
3
H
D
C
4
4
P
4
5
4
5
P
4
6
4
6
P
4
7
4
7
L
D
C
4
8
N
C
4
9
N
C
5
0
G
N
D
5
1
P
5
2
5
2
P
5
3
5
3
P
5
4
5
4
P
5
5
5
5
P
5
6
5
6
P
5
7
5
7
P
5
8
5
8
I
N
I
T
5
9
V
C
C
6
0
G
N
D
6
1
P
6
2
6
2
P
6
3
6
3
P
6
4
6
4
P
6
5
6
5
P
6
6
6
6
P
6
7
6
7
P
6
8
6
8
P
6
9
6
9
G
N
D
7
0
N
C
7
1
N
C
7
2
P
7
3
7
3
P
7
4
7
4
P
7
5
7
5
P
7
6
7
6
P
7
7
7
7
P
7
8
7
8
G
N
D
7
9
D
O
N
E
8
0
VCC
81
PROG
82
D7+
83
P84
84
P85
85
P86
86
D6+
87
P88
88
NC
89
NC
90
GND
91
P92
92
P93
93
D5+
94
CSO+
95
P96
96
P97
97
D4+
98
P99
99
VCC
100
GND
101
D3+
102
RS+
103
P104
104
P105
105
D2+
106
P107
107
P108
108
P109
109
GND
110
NC
111
NC
112
D1+
113
RCLK+
114
P115
115
P116
116
D0/DIN
117
DOUT+
118
CCLK
119
VCC
120
T
D
O
1
2
1
G
N
D
1
2
2
A
0
/
W
S
+
1
2
3
A
1
+
1
2
4
P
1
2
5
1
2
5
P
1
2
6
1
2
6
A
2
/
C
S
1
+
1
2
7
A
3
+
1
2
8
N
C
1
2
9
N
C
1
3
0
G
N
D
1
3
1
P
1
3
2
1
3
2
P
1
3
3
1
3
3
A
4
+
1
3
4
A
5
+
1
3
5
N
C
1
3
6
P
1
3
7
1
3
7
P
1
3
8
1
3
8
A
6
+
1
3
9
A
7
+
1
4
0
G
N
D
1
4
1
V
C
C
1
4
2
A
8
+
1
4
3
A
9
+
1
4
4
P
1
4
5
1
4
5
P
1
4
6
1
4
6
A
1
0
+
1
4
7
A
1
1
+
1
4
8
P
1
4
9
1
4
9
P
1
5
0
1
5
0
G
N
D
1
5
1
N
C
1
5
2
N
C
1
5
3
A
1
2
+
1
5
4
A
1
3
+
1
5
5
P
1
5
6
1
5
6
P
1
5
7
1
5
7
A
1
4
+
1
5
8
A
1
5
+
1
5
9
V
C
C
1
6
0
U29
XC4005PQ160-4PC
P
_
A
0
P
_
A
1
P
_
A
2
P
_
A
3
P
_
A
4
P
_
A
5
P
_
A
6
P
_
A
7
P
_
A
8
P
_
A
9
P
_
A
1
0
P
_
A
1
1
P
_
A
1
2
P
_
A
1
3
P
_
A
1
4
P
_
A
1
5
V
C
C
V
C
C
G
N
D
G
N
D
SPARE I/O
APB SIGNALS
1
V92
1
V94
1
V95
P_D[31..0]
P_A[31..0]
P_WRITE
P_STB
P_SELIC
P_SELCT
P_SELRC
P_SELEX
B_RES[2..0]
B_CLK0
GND
P_A[31..0]
P_D[31..0]
P_WRITE
P_STB
P_SELIC
P_SELCT
P_SELRC
P_SELEX
B_RES[2..0]
B_CLK0
B_CLK0
INTERRUPT SOURCES
INTPCA
INTPCB
INTSPA
INTSPB
nINTPP
nFIQSRC
nINTAPB[2..0]
nINTASB[1..0]
ARMCOMMRX
ARMCOMMTX
P_D1
P_D2
P_D3
P_D4
P_D5
P_D6
P_D7
P_D8
P_D9
P_D10
P_D11
P_D12
P_D13
P_D14
P_D15
P_D16
P_D17
P_D18
P_D19
VCC
GND
GND
nINTAPB[2..0]
nFIQSRC
INTPCA
INTPCB
INTSPA
INTSPB
nINTPP
nINTASB[1..0]
ARMCOMMRX
ARMCOMMTX
SPARE I/O
1
V89
P_D20
P_D21
P_D22
P_D23
P_D24
P_D25
P_D26
P_D27
P_D28
P_D29
P_D30
P_D31
GND
GND
VCC
INTSPA
INTSPB
INTPCA
INTPCB
DIN
ARMCOMMTX
ARMCOMMRX
STANDBY =
R166
1K
REMAP
ARMnI
STANDB
Y
REMAP
ARMnIRQ
STANDBY
VCC
VCC
FPGA CON
F
SERIAL
P
DATA
1
CLK
2
OE
3
CE
4
GN
D
CE
O
VP
P
VC
C
U28
XC17128
D
9 8
U24D
74HCT14
R199
1K
DONE
DIN
CCLK
nPROG
GND
VCC
G
N
D
D
O
N
E
G
N
D
P
_
A
2
4
P
_
A
2
5
P
_
A
2
6
P
_
A
2
7
nFIQSRC
nINTPP
nINTASB0
nINTASB1
nINTAPB2
nINTAPB0
nINTAPB1
nPROG
G
N
D
V
C
C
G
N
D
V
C
C
M
O
D
E
2
P
_
A
2
8
P
_
A
2
9
P
_
A
3
0
P
_
A
3
1
P
_
S
T
B
P
_
W
R
I
T
E
P
_
S
E
L
I
C
P
_
S
E
L
C
T
P
_
S
E
L
R
C
P
_
S
E
L
E
X
I
N
I
T
R
E
M
A
P
S
T
A
N
D
B
Y
A
R
M
n
F
I
Q
A
R
M
n
I
R
Q
SPARE I/O
DOWNLOAD CABLE
CONNECTOR
1
V90
1
V91
1
V93
R162
4K7
1
2
3
4
5
6
7
8
9
J2
CON9
R167
4K7
R168
4K7
P_D0
MODE0
MODE1
B_RES0
B_RES1
B_RES2
GND
GND
CCLK
VCC
GND
DONE
VCC VCC VCC
Insert links 3-4, 5-6, 7-8
to enable serial PROM
Cut pin 3
R163
4K7
R164
4K7
R165
4K7
1
V107
+
1
+
3
+
5
+
7
+
2
+
4
+
6
+
8
LK16
LINK-4
INIT
MODE0
MODE1
MODE2
DIN
nPROG
RST
INIT
VCC VCC VCC
GND
SPARE I/O
C91
100n
C92
100n
C93
100n
C95
10u
1
V104
1
V105
1
V106
SPARE I/O
C94
100n
1
V98
1
V99
1
V100
1
V101
1
V102
1
V103
VCC
GND
DONE
VCC
GND
R160
470R
D13
LED
GRE
E
h
rg.
b
oo
k
P
age
16
W
e
d
nes
d
ay,
J
u
l
y
22
,
1998
9
:
18
AM

ARM ARM7TDMI Specifications

General

Data Width	32-bit
Cores	1
MIPS per MHz	0.9
On-chip Debug	Yes
Instruction Set	ARM
Pipeline Stages	3
Operating Voltage	Implementation dependent
Manufacturing Process	Implementation dependent