Open Access
Circuit Descriptions
3-20
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
3.2.13 APB Slaves
This schematic is shown in
A.15 APB Slaves
on page A-16.
All the APB slaves are implemented in a single Xilinx field programmable gate array (FPGA).
The XC4005 (U29) is programmed to provide the following functions:
• two 16-bit counter/timers with pre-scale
• interrupt controller
• reset and pause controller
Each of these functions is selected by accessing the appropriate address space. In addition
to P_SELCT, P_SELIC and P_SELRPC, which are the select lines for the functions above,
there is also a P_SELEX line which can be used to select user implemented functions. If you
wish to reprogram the FPGA for your own use then contact ARM for VHDL descriptions of
this device.
FPGA configuration
The FPGA is configured at power-up by a serial PROM (U28). The configuration can be
downloaded from a workstation using a special download cable connected to header (J2).
This procedure is detailed in
Chapter 9, Programming the APB FPGA
.
Link field (LK16) is used to tell the FPGA whether it is to be programmed from the serial
PROM or by download cable.
When the FPGA is successfully configured, the green LED marked “FPGA OK” lights up.
If it does not light up, check that:
• the serial PROM (U28) and the links MODE0–2 are inserted
• the device has been configured by download cable
FPGA functionality
You can program the FPGA to have different functionality by replacing the serial PROM
(U28) with an alternative device.
Position Name Description Options Default
1 INIT not used do not connect out
2 MODE0 Number of cycles out = cable, in = PROM in
3 MODE1 Selects EPROM or FLASH out = cable, in = PROM in
4 MODE2 Selects 8 or 16-bit device out = cable, in = PROM in
Table 3-12: LK16
hrg.book Page 20 Wednesday, July 22, 1998 9:18 AM
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