ARM Cortex-R4 - Page 281

Debug
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-7
ID073015 Non-Confidential
0x080 c32 RW DBGDTRRX Data Transfer Register on page 12-18
0x084 c33 W DBGITR Instruction Transfer Register on page 12-22
0x088 c34 RW DBGDSCR CP14 c1, Debug Status and Control Register on
page 12-14
0x08C c35 RW DBGDTRTX Data Transfer Register on page 12-18
0x090 c36 W DBGDRCR Debug Run Control Register on page 12-22
0x094-0x0FC c37-c63 R - RAZ
0x100-0x11C c64-c71 RW DBGBVR Breakpoint Value Registers on page 12-23
0x120-0x13C c72-c79 R - RAZ
0x140-0x15C c80-c87 RW DBGBCR Breakpoint Control Registers on page 12-24
0x160-0x17C c88-c95 R - RAZ
0x180-0x19C c96-c103 RW DBGWVR Watchpoint Value Registers on page 12-27
0x1A0-0x1BC c104-c111 R - RAZ
0x1C0-0x1DC c112-c119 RW DBGWCR Watchpoint Control Registers on page 12-28
0x1E0-0x1FC c120-c127 R - RAZ
0x200-0x2FC c128-c191 R - RAZ
0x300 c192 R DBGOSLAR Not implemented in this processor. Reads as zero.
0x304 c193 R DBGOSLSR Operating System Lock Status Register on
page 12-30
0x308 c194 R DBGOSSRR Not implemented in this processor. Reads as zero.
0x30C c195 R - RAZ
0x310 c196 RW DBGPRCR Device Power-down and Reset Control Register on
page 12-32
0x314 c197 R DBGPRSR Device Power-down and Reset Status Register on
page 12-33
0x318-0x7FC c198-c511 R - RAZ
0x800-0x8FC c512-575 R - RAZ
0x900-0xCFC c576-c831 R - RAZ
0xD00 - 0xDFC c832-c895 R - Processor ID Registers on page 12-35
0xE00 - 0xE7C c896-c927 R - RAZ
0xE80 - 0xEFC c928-c959 - - Chapter 13 Integration Test Registers
0xF00-0xFFC c960-c1023 - - Management registers on page 12-35
Table 12-3 Debug memory-mapped registers (continued)
Offset
(hex)
Register
number
Access Mnemonic Description