Debug
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-6
ID073015 Non-Confidential
The CP14 debug instructions are defined as having Opcode_1 set to 0.
12.3.4 Memory-mapped registers
Table 12-3 shows the complete list of memory-mapped registers accessible at the APB slave
interface.
You must ensure that the base address of this 4KB register map is aligned to a 4KB boundary
in physical memory.
Table 12-2 CP14 debug registers summary
Instruction Mnemonic Description
MRC p14, 0, <Rd>, c0, c0, 0
DBGDIDR Debug Identification Register.
See CP14 c0, Debug ID Register on page 12-10.
MRC p14, 0, <Rd>, c1, c0, 0
DBGDRAR Debug ROM Address Register.
See CP14 c0, Debug ROM Address Register on page 12-12.
MRC p14, 0, <Rd>, c2, c0, 0
DBGDSAR Debug Self Address Register.
See CP14 c0, Debug Self Address Offset Register on page 12-13.
MRC p14, 0, <Rd>, c0, c5, 0
STC p14, c5, <addressing mode>
DBGDTRRX Host to Target Data Transfer Register.
See Data Transfer Register on page 12-18.
MCR p14, 0, <Rd>, c0, c5, 0
LDC p14, c5, <addressing mode>
DBGDTRTX Target to Host Data Transfer Register.
See Data Transfer Register on page 12-18.
MRC p14, 0, <Rd>, c0, c1, 0
MRC p14, 0, PC, c0, c1, 0
DBGDSCR Debug Status and Control Register.
See CP14 c1, Debug Status and Control Register on page 12-14.
Table 12-3 Debug memory-mapped registers
Offset
(hex)
Register
number
Access Mnemonic Description
0x000
c0 R DBGDIDR CP14 c0, Debug ID Register on page 12-10
0x004-0x014
c1-c5 R - RAZ
0x18
c6 RW DBGWFAR Watchpoint Fault Address Register on page 12-19
0x01C
c7 RW DBGVCR Vector Catch Register on page 12-20
0x020
c8 R - RAZ
0x024
c9 RW DBGECR Not implemented in this processor. Reads as zero.
0x028
c10 RW DBGDSCCR Debug State Cache Control Register on page 12-21.
0x02C
c11 R - RAZ
0x030-0x07C
c12-c31 R - RAZ
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