Broadcom BCM7405 - Page 114

2/24/2008 9T6WP
BCM7405 Preliminary Hardware Data Module
Hardware Signal Descriptions 06/29/07
Broadcom Corporation
Page 1-100 Pin Definition Notations Document 7405-1HDM00-R
1 9 - Analog Audio/
Digital Audio
AUD0_RIGHT
_p
AO – 2.5 – B21 Right audio differential
output (6mA 2.5V, 13.5
MHz)
1 9 - Analog Audio/
Digital Audio
AUD0_RIGHT
_n
AO – 2.5 – A21 Right audio differential
output (6mA 2.5V, 13.5
MHz)
1 11 - UHF/Video/HDMI/
RFM/AUDIO/...
AUD0_VDDO
25_0
APWR – 2.5 – D21 SDC isolated supply 2.5V
1 11 - UHF/Video/HDMI/
RFM/AUDIO/...
AUD0_VSSO_
0
AGND – GND – E22 SDC isolated ground
1 11 - UHF/Video/HDMI/
RFM/AUDIO/...
AUD0_VSSO_
1
AGND – GND – C22 SDC isolated ground
1 11 - UHF/Video/HDMI/
RFM/AUDIO/...
AUD0_VSSO_
2
AGND – GND – E21 SDC isolated ground
1 11 - UHF/Video/HDMI/
RFM/AUDIO/...
AUD0_VDDO
25_1
APWR – 2.5 – D22 SDC isolated supply 2.5V
Bus Connections
System DDR-DRAM Interface – 157
1 11 - UHF/Video/HDMI/
RFM/AUDIO/...
DDR_BVDD0 I/O Ext PU SSTL
_18
– AL6 DDR 1.2 V analog voltage
1 11 - UHF/Video/HDMI/
RFM/AUDIO/ …
DDR_BVDD1 I/O Ext PU SSTL
_18
– C6 DDR 1.2 V analog voltage
1 11 - UHF/Video/HDMI/
RFM/AUDIO/...
DDR_BVSS0 I/O Ext PU SSTL
_18
– AK6 DDR analog ground
1 11 - UHF/Video/HDMI/
RFM/AUDIO/...
DDR_BVSS1 I/O Ext PU SSTL
_18
– D7 DDR analog ground
1 12 - Clocks DDR_PLL_TE
ST
I/O Ext PU SSTL
_18
– E7 DDR PLL test port
1 14 - 64 Bit DDR2
SDRAM
DDR01_CKE I/O Ext PU SSTL
_18
– AC5 DDR DRAM clock enable
for 16-bit lane 0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR23_CKE I/O Ext PU SSTL
_18
– G5 DDR DRAM clock enable
for 16-bit lane 2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR_NCOMP I/O Ext PU SSTL
_18
– AM6 DDR DRAM PVT N COMP
1 14 - 64 Bit DDR2
SDRAM
DDR_PCOMP I/O Ext PU SSTL
_18
– AN5 DDR DRAM PVT P COMP
1 14 - 64 Bit DDR2
SDRAM
DDR_RCOMP I/O Ext PU SSTL
_18
– AN6 DDR DRAM PVT R COMP
0 DDR_SCOMP I/O Ext PU SSTL
_18
– N/A DDR DRAM PVT S COMP
(Not bond out)
1 14 - 64 Bit DDR2
SDRAM
DDR01_ODT I/O Ext PU SSTL
_18
– AC3 DDR DRAM On Chip
Termination for 16-bit lane 0
and 1
1 14 - 64 Bit DDR2
SDRAM
DDR23_ODT I/O Ext PU SSTL
_18
– F3 DDR DRAM On Chip
Termination for 16-bit lane 2
and 3
Table 1-19: Pin Descriptions (Cont.)
# of
Pins
Orcad Schematic
Block
Label I/O Res.
Tol.
(V)
Drv.
(mA)
Loc. Description