Broadcom BCM7405 - Page 115

2/24/2008 9T6WP
Preliminary Hardware Data Module BCM7405
06/29/07 Hardware Signal Descriptions
Broadcom Corporation
Document 7405-1HDM00-R Pin Definition Notations Page 1-101
1 12 - Clocks DDR_EXT_CL
K
I/O Ext PU SSTL
_18
– E6 DDR DRAM External Clock
1 14 - 64 Bit DDR2
SDRAM
DDR0_CLK O Ext PU SSTL
_18
– AH4 DDR DRAM clocks for 16-
bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_CLKb O Ext PU SSTL
_18
– AH5 DDR DRAM clocks (low
active) for 16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR1_CLK I/O Ext PU SSTL
_18
– AC1 DDR DRAM clocks for 16-
bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_CLKb I/O Ext PU SSTL
_18
– AC2 DDR DRAM clocks (low
active) for 16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR2_CLK I/O Ext PU SSTL
_18
– M4 DDR DRAM clocks for 16-
bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_CLKb I/O Ext PU SSTL
_18
– M5 DDR DRAM clocks (low
active) for 16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR3_CLK I/O Ext PU SSTL
_18
– E1 DDR DRAM clocks for 16-
bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_CLKb I/O Ext PU SSTL
_18
– E2 DDR DRAM clocks (low
active) for 16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR01_A00 I/O Ext PU SSTL
_18
– AE5 Shared DDR DRAM
Address Bus for 16-bit lane
0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR01_A01 I/O Ext PU SSTL
_18
– AF2 Shared DDR DRAM
Address Bus for 16-bit lane
0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR01_A02 I/O Ext PU SSTL
_18
– AE4 Shared DDR DRAM
Address Bus for 16-bit lane
0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR01_A03 I/O Ext PU SSTL
_18
– AF3 Shared DDR DRAM
Address Bus for 16-bit lane
0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR0_A04 I/O Ext PU SSTL
_18
– AJ2 Dedicated DDR DRAM
Address Bus for 16-bit lane
0
1 14 - 64 Bit DDR2
SDRAM
DDR0_A05 I/O Ext PU SSTL
_18
– AJ1 Dedicated DDR DRAM
Address Bus for 16-bit lane
0
1 14 - 64 Bit DDR2
SDRAM
DDR0_A06 I/O Ext PU SSTL
_18
– AJ3 Dedicated DDR DRAM
Address Bus for 16-bit lane
0
1 14 - 64 Bit DDR2
SDRAM
DDR01_A07 I/O Ext PU SSTL
_18
– AG3 Shared DDR DRAM
Address Bus for 16-bit lane
0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR01_A08 I/O Ext PU SSTL
_18
– AG5 Shared DDR DRAM
Address Bus for 16-bit lane
0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR01_A09 I/O Ext PU SSTL
_18
– AH2 Shared DDR DRAM
Address Bus for 16-bit lane
0 and 1
Table 1-19: Pin Descriptions (Cont.)
# of
Pins
Orcad Schematic
Block
Label I/O Res.
Tol.
(V)
Drv.
(mA)
Loc. Description