2/24/2008 9T6WP
BCM7405 Preliminary Hardware Data Module
Hardware Signal Descriptions 06/29/07
Broadcom Corporation
Page 1-102 Pin Definition Notations Document 7405-1HDM00-R
1 14 - 64 Bit DDR2
SDRAM
DDR01_A10 I/O Ext PU SSTL
_18
– AG4 Shared DDR DRAM
Address Bus for 16-bit lane
0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR01_A11 I/O Ext PU SSTL
_18
– AH3 Shared DDR DRAM
Address Bus for 16-bit lane
0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR01_A12 I/O Ext PU SSTL
_18
– AH1 Shared DDR DRAM
Address Bus for 16-bit lane
0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR01_A13 I/O Ext PU SSTL
_18
– AE3 DDR DRAM Address Bus
for 16-bit lane 0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_A04 I/O Ext PU SSTL
_18
– AF5 Dedicated DDR DRAM
Address Bus for 16-bit lane
1
1 14 - 64 Bit DDR2
SDRAM
DDR1_A05 I/O Ext PU SSTL
_18
– AG2 Dedicated DDR DRAM
Address Bus for 16-bit lane
1
1 14 - 64 Bit DDR2
SDRAM
DDR1_A06 I/O Ext PU SSTL
_18
– AF4 Dedicated DDR DRAM
Address Bus for 16-bit lane
1
1 14 - 64 Bit DDR2
SDRAM
DDR23_A00 I/O Ext PU SSTL
_18
– J5 Shared DDR DRAM
Address Bus for 16-bit lane
2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR23_A01 I/O Ext PU SSTL
_18
– H2 Shared DDR DRAM
Address Bus for 16-bit lane
2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR23_A02 I/O Ext PU SSTL
_18
– J4 Shared DDR DRAM
Address Bus for 16-bit lane
2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR23_A03 I/O Ext PU SSTL
_18
– J3 Shared DDR DRAM
Address Bus for 16-bit lane
2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR2_A04 I/O Ext PU SSTL
_18
– L2 Dedicated DDR DRAM
Address Bus for 16-bit lane
2
1 14 - 64 Bit DDR2
SDRAM
DDR2_A05 I/O Ext PU SSTL
_18
– L1 Dedicated DDR DRAM
Address Bus for 16-bit lane
2
1 14 - 64 Bit DDR2
SDRAM
DDR2_A06 I/O Ext PU SSTL
_18
– M2 Dedicated DDR DRAM
Address Bus for 16-bit lane
2
1 14 - 64 Bit DDR2
SDRAM
DDR23_A07 I/O Ext PU SSTL
_18
– K3 Shared DDR DRAM
Address Bus for 16-bit lane
2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR23_A08 I/O Ext PU SSTL
_18
– L5 Shared DDR DRAM
Address Bus for 16-bit lane
2 and 3
Table 1-19: Pin Descriptions (Cont.)
# of
Pins
Orcad Schematic
Block
Label I/O Res.
Tol.
(V)
Drv.
(mA)
Loc. Description