Broadcom BCM7405 - Page 117

2/24/2008 9T6WP
Preliminary Hardware Data Module BCM7405
06/29/07 Hardware Signal Descriptions
Broadcom Corporation
Document 7405-1HDM00-R Pin Definition Notations Page 1-103
1 14 - 64 Bit DDR2
SDRAM
DDR23_A09 I/O Ext PU SSTL
_18
– K2 Shared DDR DRAM
Address Bus for 16-bit lane
2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR23_A10 I/O Ext PU SSTL
_18
– L4 Shared DDR DRAM
Address Bus for 16-bit lane
2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR23_A11 I/O Ext PU SSTL
_18
– L3 Shared DDR DRAM
Address Bus for 16-bit lane
2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR23_A12 I/O Ext PU SSTL
_18
– K1 Shared DDR DRAM
Address Bus for 16-bit lane
2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR23_A13 I/O Ext PU SSTL
_18
– H3 DDR DRAM Address Bus
for 16-bit lane 2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_A04 I/O Ext PU SSTL
_18
– K5 Dedicated DDR DRAM
Address Bus for 16-bit lane
3
1 14 - 64 Bit DDR2
SDRAM
DDR3_A05 I/O Ext PU SSTL
_18
– J2 Dedicated DDR DRAM
Address Bus for 16-bit lane
3
1 14 - 64 Bit DDR2
SDRAM
DDR3_A06 I/O Ext PU SSTL
_18
– K4 Dedicated DDR DRAM
Address Bus for 16-bit lane
3
1 14 - 64 Bit DDR2
SDRAM
DDR01_BA0 I/O Ext PU SSTL
_18
– AE2 DDR DRAM Bank Address
for 16-bit lane 0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR01_BA1 I/O Ext PU SSTL
_18
– AD4 DDR DRAM Bank Address
for 16-bit lane 2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR01_BA2 I/O Ext PU SSTL
_18
– AD5 DDR DRAM Bank Address
for 16-bit lane 0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR23_BA0 I/O Ext PU SSTL
_18
– G2 DDR DRAM Bank Address
for 16-bit lane 0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR23_BA1 I/O Ext PU SSTL
_18
– H4 DDR DRAM Bank Address
for 16-bit lane 2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR23_BA2 I/O Ext PU SSTL
_18
– H5 DDR DRAM Bank Address
for 16-bit lane 2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR01_CASb I/O Ext PU SSTL
_18
– AC4 DDR DRAM CAS signal for
16-bit lane 0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR23_CASb I/O Ext PU SSTL
_18
– G4 DDR DRAM CAS signal for
16-bit lane 2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ00 I/O Ext PU SSTL
_18
– AK2 DDR DRAM Data bus for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ01 I/O Ext PU SSTL
_18
– AN3 DDR DRAM Data bus for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ02 I/O Ext PU SSTL
_18
– AL3 DDR DRAM Data bus for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ03 I/O Ext PU SSTL
_18
– AM2 DDR DRAM Data bus for
16-bit lane 0
Table 1-19: Pin Descriptions (Cont.)
# of
Pins
Orcad Schematic
Block
Label I/O Res.
Tol.
(V)
Drv.
(mA)
Loc. Description