Broadcom BCM7405 - Page 118

2/24/2008 9T6WP
BCM7405 Preliminary Hardware Data Module
Hardware Signal Descriptions 06/29/07
Broadcom Corporation
Page 1-104 Pin Definition Notations Document 7405-1HDM00-R
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ04 I/O Ext PU SSTL
_18
– AP4 DDR DRAM Data bus for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ05 I/O Ext PU SSTL
_18
– AJ5 DDR DRAM Data bus for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ06 I/O Ext PU SSTL
_18
– AN4 DDR DRAM Data bus for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ07 I/O Ext PU SSTL
_18
– AJ4 DDR DRAM Data bus for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ08 I/O Ext PU SSTL
_18
– AK3 DDR DRAM Data bus for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ09 I/O Ext PU SSTL
_18
– AN2 DDR DRAM Data bus for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ10 I/O Ext PU SSTL
_18
– AL2 DDR DRAM Data bus for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ11 I/O Ext PU SSTL
_18
– AM3 DDR DRAM Data bus for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ12 I/O Ext PU SSTL
_18
– AP3 DDR DRAM Data bus for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ13 I/O Ext PU SSTL
_18
– AK5 DDR DRAM Data bus for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ14 I/O Ext PU SSTL
_18
– AP2 DDR DRAM Data bus for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQ15 I/O Ext PU SSTL
_18
– AK4 DDR DRAM Data bus for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ00 I/O Ext PU SSTL
_18
– AB4 DDR DRAM Data bus for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ01 I/O Ext PU SSTL
_18
– V5 DDR DRAM Data bus for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ02 I/O Ext PU SSTL
_18
– AA5 DDR DRAM Data bus for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ03 I/O Ext PU SSTL
_18
– Y4 DDR DRAM Data bus for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ04 I/O Ext PU SSTL
_18
– U3 DDR DRAM Data bus for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ05 I/O Ext PU SSTL
_18
– AB3 DDR DRAM Data bus for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ06 I/O Ext PU SSTL
_18
– V2 DDR DRAM Data bus for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ07 I/O Ext PU SSTL
_18
– AB1 DDR DRAM Data bus for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ08 I/O Ext PU SSTL
_18
– AB5 DDR DRAM Data bus for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ09 I/O Ext PU SSTL
_18
– V4 DDR DRAM Data bus for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ10 I/O Ext PU SSTL
_18
– AA4 DDR DRAM Data bus for
16-bit lane 1
Table 1-19: Pin Descriptions (Cont.)
# of
Pins
Orcad Schematic
Block
Label I/O Res.
Tol.
(V)
Drv.
(mA)
Loc. Description