Broadcom BCM7405 - Page 119

2/24/2008 9T6WP
Preliminary Hardware Data Module BCM7405
06/29/07 Hardware Signal Descriptions
Broadcom Corporation
Document 7405-1HDM00-R Pin Definition Notations Page 1-105
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ11 I/O Ext PU SSTL
_18
– W4 DDR DRAM Data bus for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ12 I/O Ext PU SSTL
_18
– V3 DDR DRAM Data bus for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ13 I/O Ext PU SSTL
_18
– AB2 DDR DRAM Data bus for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ14 I/O Ext PU SSTL
_18
– W2 DDR DRAM Data bus for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQ15 I/O Ext PU SSTL
_18
– AA3 DDR DRAM Data bus for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ00 I/O Ext PU SSTL
_18
– M3 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ01 I/O Ext PU SSTL
_18
– U2 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ02 I/O Ext PU SSTL
_18
– P2 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ03 I/O Ext PU SSTL
_18
– P3 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ04 I/O Ext PU SSTL
_18
– U1 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ05 I/O Ext PU SSTL
_18
– N5 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ06 I/O Ext PU SSTL
_18
– U4 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ07 I/O Ext PU SSTL
_18
– N4 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ08 I/O Ext PU SSTL
_18
– N2 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ09 I/O Ext PU SSTL
_18
– T3 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ10 I/O Ext PU SSTL
_18
– N3 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ11 I/O Ext PU SSTL
_18
– R3 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ12 I/O Ext PU SSTL
_18
– T1 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ13 I/O Ext PU SSTL
_18
– P5 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ14 I/O Ext PU SSTL
_18
– U5 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQ15 I/O Ext PU SSTL
_18
– P4 DDR DRAM Data bus for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ00 I/O Ext PU SSTL
_18
– F4 DDR DRAM Data bus for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ01 I/O Ext PU SSTL
_18
– F5 DDR DRAM Data bus for
16-bit lane 3
Table 1-19: Pin Descriptions (Cont.)
# of
Pins
Orcad Schematic
Block
Label I/O Res.
Tol.
(V)
Drv.
(mA)
Loc. Description