Broadcom BCM7405 - Page 120

2/24/2008 9T6WP
BCM7405 Preliminary Hardware Data Module
Hardware Signal Descriptions 06/29/07
Broadcom Corporation
Page 1-106 Pin Definition Notations Document 7405-1HDM00-R
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ02 I/O Ext PU SSTL
_18
– D3 DDR DRAM Data bus for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ03 I/O Ext PU SSTL
_18
– D4 DDR DRAM Data bus for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ04 I/O Ext PU SSTL
_18
– B5 DDR DRAM Data bus for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ05 I/O Ext PU SSTL
_18
– D2 DDR DRAM Data bus for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ06 I/O Ext PU SSTL
_18
– B4 DDR DRAM Data bus for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ07 I/O Ext PU SSTL
_18
– C2 DDR DRAM Data bus for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ08 I/O Ext PU SSTL
_18
– E3 DDR DRAM Data bus for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ09 I/O Ext PU SSTL
_18
– C5 DDR DRAM Data bus for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ10 I/O Ext PU SSTL
_18
– E4 DDR DRAM Data bus for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ11 I/O Ext PU SSTL
_18
– E5 DDR DRAM Data bus for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ12 I/O Ext PU SSTL
_18
– A4 DDR DRAM Data bus for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ13 I/O Ext PU SSTL
_18
– B1 DDR DRAM Data bus for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ14 I/O Ext PU SSTL
_18
– C4 DDR DRAM Data bus for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQ15 I/O Ext PU SSTL
_18
– B2 DDR DRAM Data bus for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR0_DM0 I/O Ext PU SSTL
_18
– AN1 DDR DRAM Data Mask for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DM1 I/O Ext PU SSTL
_18
– AP1 DDR DRAM Data Mask for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR1_DM0 I/O Ext PU SSTL
_18
– Y5 DDR DRAM Data Mask for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DM1 O Ext PU SSTL
_18
– W5 DDR DRAM Data Mask for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR2_DM0 O Ext PU SSTL
_18
– R2 DDR DRAM Data Mask for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DM1 O Ext PU SSTL
_18
– T2 DDR DRAM Data Mask for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR3_DM0 O Ext PU SSTL
_18
– C3 DDR DRAM Data Mask for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DM1 O Ext PU SSTL
_18
– D5 DDR DRAM Data Mask for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQS0 O Ext PU SSTL
_18
– AM4 DDR DRAM Data Strobe for
16-bit lane 0
Table 1-19: Pin Descriptions (Cont.)
# of
Pins
Orcad Schematic
Block
Label I/O Res.
Tol.
(V)
Drv.
(mA)
Loc. Description