Broadcom BCM7405 - Page 121

2/24/2008 9T6WP
Preliminary Hardware Data Module BCM7405
06/29/07 Hardware Signal Descriptions
Broadcom Corporation
Document 7405-1HDM00-R Pin Definition Notations Page 1-107
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQS0b O Ext PU SSTL
_18
– AM5 DDR DRAM Data Strobe
(low active) for 16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQS1 O Ext PU SSTL
_18
– AL4 DDR DRAM Data Strobe for
16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR0_DQS1b I/O Ext PU SSTL
_18
– AL5 DDR DRAM Data Strobe
(low active) for 16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQS0 I/O Ext PU SSTL
_18
– W3 DDR DRAM Data Strobe for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQS0b I/O Ext PU SSTL
_18
– Y2 DDR DRAM Data Strobe
(low active) for 16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQS1 I/O Ext PU SSTL
_18
– Y3 DDR DRAM Data Strobe for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR1_DQS1b I/O Ext PU SSTL
_18
– AA2 DDR DRAM Data Strobe
(low active) for 16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQS0 I/O Ext PU SSTL
_18
– T4 DDR DRAM Data Strobe for
16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQS0b I/O Ext PU SSTL
_18
– T5 DDR DRAM Data Strobe
(low active) for 16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQS1 I/O Ext PU SSTL
_18
– R4 DDR DRAM Data Strobe for
16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR2_DQS1b I/O Ext PU SSTL
_18
– R5 DDR DRAM Data Strobe
(low active) for 16-bit lane 2
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQS0 I/O Ext PU SSTL
_18
– A3 DDR DRAM Data Strobe for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQS0b I/O Ext PU SSTL
_18
– B3 DDR DRAM Data Strobe
(low active) for 16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQS1 I/O Ext PU SSTL
_18
– A2 DDR DRAM Data Strobe for
16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR3_DQS1b I/O Ext PU SSTL
_18
– A1 DDR DRAM Data Strobe
(low active) for 16-bit lane 3
1 14 - 64 Bit DDR2
SDRAM
DDR01_RASb I/O Ext PU SSTL
_18
– AD3 DDR DRAM RAS signal for
16-bit lane 0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR23_RASb I/O Ext PU SSTL
_18
– G3 DDR DRAM RAS signal for
16-bit lane 2 and 3
1 14 - 64 Bit DDR2
SDRAM
DDR_VREF0 I/O Ext PU SSTL
_18
– AP5 DDR DRAM voltage
reference for 16-bit lane 0
1 14 - 64 Bit DDR2
SDRAM
DDR_VREF1 O Ext PU SSTL
_18
– A6 DDR DRAM voltage
reference for 16-bit lane 1
1 14 - 64 Bit DDR2
SDRAM
DDR01_WEb O Ext PU SSTL
_18
– AD2 DDR DRAM WEB for 16-bit
lane 0 and 1
1 14 - 64 Bit DDR2
SDRAM
DDR23_WEb O Ext PU SSTL
_18
– F2 DDR DRAM WEB for 16-bit
lane 2 and 3
PCI Bus – 55
1 1 - PCI Bus/EBI PCI_AD00 I/O Ext PU 3.3 – AP20 PCI Address / Data bus.
Shared with EBI_DATA0
Table 1-19: Pin Descriptions (Cont.)
# of
Pins
Orcad Schematic
Block
Label I/O Res.
Tol.
(V)
Drv.
(mA)
Loc. Description