Caen V2718 - Block Diagram; Fig. 1: Mod. V2718 Block Diagram

Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V2718 VME PCI Optical Link Bridge
03/07/2018
11
NPO:
Filename:
Number of pages:
Page:
00106/03:V2718.MUTx/11
V2718_REV11.DOC
79
10
1.2. Block diagram
128K SRAM
BUFFER
VME BUS
V2718
A2719
CONET
INTERF.
FPGA
MASTER
SLAVE
SYSTEM
CONTROLLER
RAM
16x32
VME CYCLE
MONITOR
LOCAL BUS
INTERFACE
I/O
CONTROL
NIM/TTL
I/Os
DATA-WAY
DISPLAY
x5
x2
x88
uC
4Mbit FLASH
(FPGA FIRMWARE +
USER DEFINED)
BOOT
LOAD
STD
BCK
FW
A2818
LOCAL BUS
INTERFACE
PCI BUS
FPGA
PLX-9054
PCI
INTERFACE
256K SRAM
BUFFER
4Mbit FLASH
(FPGA FIRMWARE +
USER DEFINED)
STD
BCK
FW
uC
BOOT
LOAD
CONET
Optical Fiber
Fig. 1: Mod. V2718 block diagram
The FPGA (Field Programmable Gate Array) is the module’s core; it implements the
CONET communication protocol, the LED display and I/O connectors management on
the front side and the VME Master on the backside.
A 128 kbyte buffer allows to provide a temporary data storage during VME cycles: the
VME data rate is thus decoupled from the PCI rate and may take place at full speed.