Caen V2718 - Input Register; Output Set Register; Fig. 11: Input Register; Fig. 12: Output Set Register

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User's Manual (MUT)

Mod. V2718 VME PCI Optical Link Bridge

03/07/2018

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00106/03:V2718.MUTx/11

V2718_REV11.DOC

2.13.8. Input register

(Base Address + 0x08, D16, read/write)

This register carries the input register pattern.

Fig. 11: Input register

2.13.9. Output set register

(Base Address + 0x0A, D16, read/write)

This register allows to set the output register pattern: 1 = set; 0 = leave previous setting

Fig. 12: Output set register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IN0

IN1

IN0_OR_IN1

PLSA_OUT

PLSB_OUT

SCR_END_CNT_PLS

LMON

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLSA_START

PLSA_RESET

SCR_GATE

SCR_RESET

OUT0

PLSB_START

PLSB_RESET

OUT1

OUT2

OUT3

OUT4

Main Page

Table of Contents3
General Description8
- Overview8
- Block Diagram10
- Fig. 1: Mod. V2718 Block Diagram10
- Conet Layout11
- Fig. 2: CONET Cables Layout11
Vme Interface12
- Vme Bus Requester12
- Fig. 3: Internal Arbitration for VME Bus Requests12
  - Fair and Demand Request Modes13
  - VME Bus Release13
- Addressing Capabilities13
- Data Transfer Capabilities14
- Interrupt Capabilities14
- Cycle Terminations15
- Slave16
Fig. 4: V2718 Slave Operation16
- Location Monitor17
- Vme Bus First Slot Detector17
- System Controller Functions18
  - System Clock Driver18
  - Arbitration Module18
    - Fixed Priority Arbitration Mode (PRI)18
    - Round Robin Arbitration Mode (RRS)18
- Bus Timer18
- Iack Daisy Chain Driver19
- Vme64X Cycles Not yet Implemented19
- Internal Registers20
  - Status Register21
Fig . 5: the Location Monitor21
Fig. 6: Status Register21
- Egister21
  - Control Register22
  - Firmware Revision Register22
Fig. 7: Control Register22
- Firmware Download Register23
- Flash Enable Register23
- IRQ Status Register23
- IRQ Mask Register23
Fig . 8: Firmware Revisionr23
Fig. 9: IRQ Status Register23
Fig. 10: IRQ Mask Register23
- Input Register24
- Output Set Register24
Fig. 11: Input Register24
Fig. 12: Output Set Register24
- Output Clear Register25
Fig. 13: Output Set Register25
- Input Multiplexer Set Register26
Fig. 14: Input Multiplexer Register26
- Input Multiplexer Clear Register27
Fig. 15: Input Multiplexer Register27
- Output Multiplexer Set Register28
- Set Register28
- Output Multiplexer Clear Register29
- LED Polarity Set Register29
Fig . 16: Output Multiplexer29
Fig . 17: Output Multiplexer29
Fig. 18: LED Polarity Set Register29
- Set Register29
- LED Polarity Clear Register30
- Pulser a 0 Register30
- Pulser a 1 Register30
Fig. 19: LED Polarity Clear Register30
Fig . 20: Pulsera 0 Register30
Fig . 21: Pulsera 1 Register30
- Pulser B 0 Register31
- Pulser B 1 Register31
- Scaler 0 Register31
Fig . 22: Pulserb 0 Register31
Fig . 23: Pulserb 1 Register31
Fig . 24: Scaler Register31
- Scaler 1 Register32
- Display Address Low Register32
- Display Address High Register32
- Display Data Low Register32
Fig. 25: Scaler 1 Register32
Fig . 26: Display Addressl32
Fig . 27: Display Addressh32
Fig . 28: Display Addressl32
- Ow Register32
- Igh Register32
Fig . 29: Display Datah33
Fig . 30: Display Controll33
Fig . 31: Display Controll33
- Igh Register33
- Eft Register33
Fig . 32: Location Monitor34
Fig . 33: Location Monitor34
Onitor Control Register34
- Status Register34
Fig . 35: Ba Rotary Switches34
- Address Low Register34
Technical Specifications35
- Packaging35
- Power Requirements35
- Front Panel36
Fig . 36: Mod . V2718 and Fig . 37: Prog_3 Switch Setting36
- V2718 and A2818/A3818 External Components37
- V2718 Internal Hardware Components38
  - Switches38
  - Internal Jumpers40
Fig. 38: Component Location40
- Programmable Input/Output41
- I/Ointernal Connections43
Fig . 39: Input /O43
- Utput Connections Scheme43
- Vme Dataway Display44
Fig. 40: Dataway Display Layout44
- Firmware Upgrade46
Fig . 41: Caenu Pgrader ' S "G46
- Fw Release " View46
Fig . 42: Caenu Pgrader ' S "U47
Fig . 43: Vme Index in the Fig . 44: Firmware Revision on the47
- Dataway Display48
- V2718 Technical Specifications Table49
Software Overview50
- Software User Interface50
  - Software User Interface: Installation50
Fig . 45: the Software & D50
- Introduction50
- Hardware Installation51
- CAENVME Demo: the Main Menu52
Fig. 46: the Main Menu52
- Software User Interface: I/O Setting Menu - VME Settings53
- Software User Interface: I/O Setting Menu - Pulser53
Fig . 47: the I/O Setting Menu53
Fig . 48: the I/O Setting Menu53
- Vme Settings53
- Software User Interface: I/O Setting Menu - Scaler54
- Software User Interface: I/O Setting Menu - Location Monitor54
Fig . 49: the I/O Setting Menu54
Fig . 50: the I/O Setting Menu54
- Scaler54
- Location Monitor54
- Software User Interface: I/O Setting Menu - Input55
- Software User Interface: I/O Setting Menu - Output55
- Software User Interface: I/O Setting Menu - Display55
Fig . 51: the I/O Setting Menu55
Fig . 52: the I/O Setting Menu55
Fig . 53: the I/O Setting Menu55
- Input55
- Software User Interface: I/O Setting Menu - about56
- Caenvmelib Introduction56
- Caenvmelib 1.X Description56
  - Caenvme_Swrelease56
Fig . 54: the I/O Setting Menu56
- Caenvme_Init57
- Caenvme_Boardfwrelease57
- Caenvme_End57
- Caenvme_Readcycle58
- Caenvme_Multiread58
- Caenvme_Rmwcycle59
- Caenvme_Writecycle59
- Caenvme_Multiwrite60
- Caenvme_Bltreadcycle60
- Caenvme_Mbltreadcycle61
- Caenvme_Bltwritecycle61
- Caenvme_Mbltwritecycle62
- Caenvme_Adocycle62
- Caenvme_Adohcycle62
- Caenvme_Setpulserconf63
- Caenvme_Setscalerconf64
- Caenvme_Setoutputconf65
- Caenvme_Setinputconf65
Technical Support79

Caen V2718 - Input Register; Output Set Register; Fig. 11: Input Register; Fig. 12: Output Set Register

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