Caen V2718 - I;Ointernal Connections; Fig. 39: Input;O; Utput Connections Scheme

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Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V2718 VME PCI Optical Link Bridge
03/07/2018
11
NPO:
Filename:
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Page:
00106/03:V2718.MUTx/11
V2718_REV11.DOC
79
43
3.7. I/O internal connections
Fig. 39: Input/Output connections scheme
IN0
IMX[0]
IN1
0
1
0
1
0
1
00
01
10
11
IMX[1]
IMX[2]
OR[0]
IMX[4:3]
0
1
IMX[5]
OR[2]
STARTA
RESETA
PULSER-A
OUTPA
TA
WA
NA
RNGA
00
01
10
11
OR[1]
IMX[7:6]
0
1
IMX[8]
OR[3]
STARTB
RESETB
PULSER-B
OUTPB
TB
WB
NB
RNGB
0
1
IMX[11]
OR[5]
HIT
RES
SCALER
END_CNT
PULSE
END_CNT
LIMIT
AUTORES
0
1
IMX[10]
0
1
IMX[9]
OR[4]
GATE
00
01
10
11
OR[6]
OMX[1:0]
0
1
OMX[10]
O0-DS
LOC. MON.
VMON
LMADL
LMADH
LMC
AD
AM
WRITE
LWORD
IACK
DS0
DS1
VME BUS
IN0_OR_IN1
00
01
10
11OR[7]
OMX[3:2]
0
1
OMX[11]
O1-AS
AS
00
01
10
11OR[8]
OMX[5:4]
0
1
OMX[12]
O2-DTK
DTACK
00
01
10
11OR[9]
OMX[7:6]
0
1
OMX[13]
O3-BERR
BERR
00
01
10
11OR[10]
OMX[9:8]
0
1
OMX[14]
O4-VMON
IR[6:0]
INPUT0
INPUT1
SYSRES
PUSHBUTTON
/AS
LPOL[6]
0
1
LPOL[5]
0
1
LPOL[0]
0
1
LPOL[1]
0
1
LPOL[2]
0
1
LPOL[3]
0
1
LPOL[4]
0
1
0 1 2 3 4 5 6
IMX = Input MUX
OMX = Output MUX
IR = Input Register
OR = Input Register
LPOL = LED Polarity