D64 for MBLT
− BLT/MBLT cycles may be performed with either address increment or with fixed
address (FIFO mode)
− BLT/MBLT cycles are split at hardware level when the boundary (BLT = Nx256 bytes;
MBLT = Nx2 Kbytes) is met: AS is released and then re-asserted, the VME bus is not
re-arbitered. The boundaries are neglected in FIFO operating mode.
− Non aligned accesses are not supported.
It is then possible to perform data cycles (single and BLT) with hardware byte swapping.
The “Swapped” cycles are called: D16_swapped, D32_swapped and D64_swapped.
Such cycles will return “swapped” data, in the following way:
D16_swapped: Byte0 ↔ Byte1, Byte1 ↔ Byte0
D32_swapped: Byte0 ↔ Byte3, Byte1 ↔ Byte2, Byte2 ↔ Byte1, Byte3 ↔ Byte0
D32_swapped: Byte0 ↔ Byte7, Byte1 ↔ Byte6, Byte2 ↔ Byte5, Byte3 ↔ Byte4, Byte4 ↔
Byte3, Byte5 ↔ Byte2, Byte6 ↔ Byte1, Byte7 ↔ Byte0
2.4. Interrupt capabilities
The VME Bus interrupts are transferred to the PCI BUS through the CONET. The
interrupt latency (i.e. the interval between the interrupt appearance on the VME bus and
the time the interrupt is activated on the PCI bus) is always shorter than 5 µs.
The V2718 supports the following IACK cycles:
IACK: D08, D16, D32
VME Bus Interrupts can be individually masked for each V2718 in the chain.
In order to enable the generation of PCI bus interrupts following VME bus interrupts, the
IRQEnable function (see § 4.3.48) must be used; then it is necessary to call IRQWait
(see § 4.3.50) in order to wait for the interrupt. When the IRQWait function returns, the
VME bus interrupts are disabled, so an IACK can be performed in order to obtain the
vector and, for RORA interrupts, the access to the interrupter must be performed in order
to stop the interrupt generation. If it is necessary to receive other VME bus interrupts, the
IRQEnable must be called again.
To Next Page
Loading...