2.13.4. Firmware Download register
(Base Address + 0x03, D16, read/write)
This register is reserved for internal use only.
2.13.5. Flash Enable register
(Base Address + 0x04, D16, read/write)
This register is reserved for internal use only.
2.13.6. IRQ Status register
(Base Address + 0x05, D16, read only)
This register allows to monitor the IRQ lines status (1 = Active, 0 = Inactive).
Fig. 9: IRQ Status register
2.13.7. IRQ Mask register
(Base Address + 0x06, D16, read/write)
This register allows to mask the IRQ lines (1 = Masked, 0 = Unmasked). If one line is
masked, the interrupt on the VME bus is not transmitted to the PCI bus.
Fig. 10: IRQ Mask register
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