REG:2F:18 – EVC_HPW – Half Period Warning Counter
The bits of the EVC_HPW register are described below:
Description of fields within Sub-Register 0x2F:18 – Half Period Warning Counter
EVC_HPW
reg:2F:18
bits:11–0
Half Period Warning Event Counter. The EVC_HPW field is a 12-bit counter of “Half Period
Warnings”. This is a count of the reporting of the HPDWARN events in Register file: 0x0F –
System Event Status Register. These relate to late invocation of delayed transmission or
reception functionality. Please refer to the description of the HPDWARN bit for more details of
this event and its meaning. NB: For this counter to be active, counting needs to be enabled by
the setting the EVC_EN bit in Sub-Register 0x2F:00 – Event Counter Control.
The remaining bits of this register are reserved.
7.2.48.13 Sub-Register 0x2F:1A – Transmitter Power-Up Warning Counter
Transmitter Power-Up Warning Counter
Register file: 0x2F – Digital Diagnostics Interface, sub-register 0x1A is the TX Power-Up Warning Counter.
REG:2F:1A – EVC_TPW – Transmitter Power-Up Warning Counter
The bits of the EVC_TPW register are described below:
Description of fields within Sub-Register 0x2F:1A – Transmitter Power-Up Warning Counter
EVC_TPW
reg:2F:1A
bits:11–0
TX Power-Up Warning Event Counter. The EVC_TPW field is a 12-bit counter of “Transmitter
Power-Up Warnings”. This is a count of the reporting of the TXPUTE events in Register file:
0x0F – System Event Status Register. These relate to a delayed sent time that is too short to
allow proper power up of the TX blocks before the delayed transmission is due to start. Please
refer to the description of the TXPUTE bit for more details of this event.
NB: For this counter to be active, counting needs to be enabled by the setting the EVC_EN bit
in Sub-Register 0x2F:00 – Event Counter Control.
The remaining bits of this register are reserved.
7.2.48.14 Sub-Register 0x2F:1C – EVC_RES1
Digital Diagnostics Reserved Area 1
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