Signal Name FPGA/PS Pin Remarks
FPGA_LED0# H7 User function/active-low
FPGA_LED1# H6 User function/active-low
FPGA_LED2# H9 User function/active-low
MDIO_SEL_LED3# MIO15 User function/active-low; shared with MDIO select signal
Table 20: LEDs
Note that MIO15 is a dual-function pin and by changing the value of this signal, the MDIO/I2C selection
circuit is also affected - please refer to Section 2.9.8 for details on the usage of this pin.
2.15 DDR3 SDRAM (PS)
There are two DDR3 SDRAM channels on the Mercury ZX1 SoC module: one attached directly to the PS side
(which is available only as a shared resource to the PL side) and one attached directly to the PL side.
The DDR3 SDRAM connected to the PS is operated at 1.35 V (low power mode) or at 1.5 V, depending on a
selection signal. Two 16-bit memory chips are used to build a 32-bit wide memory.
The maximum memory bandwidth on the Mercury ZX1 SoC module for the DDR3 SDRAM (PS) is:
1066 Mbit/sec × 32 bit = 4264 MB/sec
2.15.1 DDR3 SDRAM Type
Table 21 describes the memory availability and configuration on the Mercury ZX1 SoC module.
Module SDRAM Type Density Configuration Manufacturer
ME-ZX1-D10 (commercial) NT5CC256M16CP-DI 4 Gbit 256 M × 16 bit Nanya
ME-ZX1-D10 (industrial) NT5CC256M16CP-DII 4 Gbit 256 M × 16 bit Nanya
ME-ZX1-D10 (industrial) NT5CC256M16ER-EKI 4 Gbit 256 M × 16 bit Nanya
ME-ZX1-D10 (industrial) K4B4G1646D-BMK0 4 Gbit 256 M × 16 bit Samsung
ME-ZX1-D10 (industrial) K4B4G1646E-BMMA 4 Gbit 256 M × 16 bit Samsung
ME-ZX1-D10 (industrial) H5TC4G63CFR-RDI 4 Gbit 256 M × 16 bit SK Hynix
Table 21: DDR3 SDRAM (PS) Types
Warning!
Other DDR3 memory devices may be equipped in future revisions of the Mercury ZX1 SoC module.
Please check the user manual regularly for updates. Any parts with different speed bins or temperature
ranges that fulfill the requirements for the module variant may be used.
D-0000-403-002 29 / 56 Version 05, 25.07.2019
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