3 Device Configuration
3.1 Configuration Signals
The PS of the SoC needs to be configured before the FPGA logic can be used. Xilinx Zynq devices need
special boot images to boot from QSPI flash or SD card. For more information, please refer to the Xilinx
Zynq-7000: Concepts, Tools, and Techniques document [20].
Table 37 describes the most important configuration pins and their location on the module connector. These
signals allow the SoC to boot from QSPI flash or SD card, and can be used to program the QSPI flash from
an external master. Please refer to Section 3.9 for details.
9
Signal SoC Mod. Description Comments
Name Pin Type Conn. Pin
FLASH_CLK MIO6 A-118 SPI CLK 20 kΩ pull-down
FLASH_DO MIO3 A-122 SPI MISO 20 kΩ pull-down
FLASH_DI MIO2 A-114 SPI MOSI 20 kΩ pull-down
FLASH_CS# MIO1 A-116 SPI CS#
10 kΩ pull-up to
VCC_CFG_MIO_B12
FPGA_DONE DONE_0 A-130 FPGA configuration done
1 kΩ pull-up to
VCC_CFG_MIO_B12
FPGA_CFGBVS CFGBVS_0 -
Configuration bank voltage select
9
10 kΩ pull-up to
VCC_CFG_MIO_B12
PS_POR# PS_POR_B A-132
Must be pulled to GND for a short
period before QSPI flash program-
ming.
10 kΩ pull-up to
PS_SRST# must be low when
PS_POR# is released.
VCC_CFG_MIO_B12
PS_SRST# PS_SRST_B A-124
Must be pulled to GND during QSPI
flash programming.
10 kΩ pull-up to
When released, all other pins of
the SPI interface must be high
impedance.
VCC_CFG_MIO_B12
BOOT_MODE0 - A-126 Boot mode selection
10 kΩ pull-up to
VCC_CFG_MIO_B12
Continued on next page...
9
The CFGBVS_0 pin is set automatically to GND (if VCC_CFG_MIO_B12 is less than or equal to 1.8 V) or to VCCO (if VCC_CFG_MIO_B12
is 2.5 V or 3.3 V).
D-0000-403-002 41 / 56 Version 05, 25.07.2019
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