Figure 10: Power-Up Sequence - VCC_IO in Relation with PWR_GOOD and PWR_EN Signals
2.9.7 Signal Terminations
Differential Inputs
There are no external differential termination resistors on the Mercury ZX1 SoC module for differential inputs.
Differential input pairs on the module connector may be terminated either by external termination resistors
on the base board (close to the module pins), or by the SoC device’s internal termination resistors.
FPGA bank 33 has two pins each equipped with a 100 Ω resistor, required for the implementation of internal
termination (DCI - Digitally Controlled Impedance).
Internal differential termination is available only for certain VCCO voltages; please refer to Xilinx AR# 43989
for details.
Single-Ended Outputs
There are no series termination resistors on the Mercury ZX1 SoC module for single-ended outputs. If
required, series termination resistors may be equipped on the base board (close to the module pins).
2.9.8 Multiplexed I/O (MIO) Pins
Details on the MIO/EMIO terminology are available in the Zynq-7000 All Programmable SoC Technical Ref-
erence Manual [18].
Some of the MIO pins on the Mercury ZX1 SoC module are connected to on-board peripherals, while others
are available as GPIOs; the suggested functions below are for reference only - always verify your MIO pinout
with the Xilinx device handbook.
Table 11 gives an overview over the MIO pin connections on the Mercury ZX1 SoC module. Only the pins
marked with “user functionality” are available on the module connector.
The MIO pins 52-53 have an external multiplexer that allows the pins to be switched either to the Ethernet
MDIO interface, or to the on-board I2C bus; by default, MDIO is selected. In order to switch to I2C operation,
MIO15 must be pulled low. Please refer to Table 10 for signal assignments.
It is recommended to use EMIO pins for I2C access. However, in situations where Ethernet is not used or
when I2C access is needed before a bitstream is loaded into the FPGA, MIO pins 52-53 may be used for I2C.
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