Enclustra Mercury ZX1 - Signal Description; Termination; Parameters; DDR3 SDRAM (PS) Parameters

2.15.2 Signal Description
Please refer to the Mercury ZX1 SoC Module FPGA Pinout Excel Sheet [4] for detailed information on the
DDR3 SDRAM connections.
2.15.3 Termination
Warning!
No external termination is implemented on the Mercury ZX1 SoC module. Therefore, it is strongly
recommended to enable the on-die termination (ODT) feature of the DDR3 SDRAM device.
2.15.4 Parameters
Please refer to the Mercury ZX1 SoC module reference design [2] for DDR3 settings guidelines. The DDR3
SDRAM parameters and the DDR3 board timing information to be set in Vivado project are presented in
Tables 22 and 23.
The values given in Table 22 are for reference only. Depending on the equipped memory device on the
Mercury ZX1 SoC module and on the DDR3 SDRAM frequency, the configuration may be different to the
one in the reference design. Please refer to the memory device datasheet for details.
Parameter Value
Memory type DDR3/DDR3L
DRAM bus width 32 bit
Operating frequency 200-533 MHz
DRAM chip bus width 16 bit
DRAM chip capacity 4096 Mbits
Speed bin DDR3_1066F
Bank bits 3
Row bits 15
Column bits 10
CAS latency 7
CAS write latency 6
RAS to CAS delay 7
Precharge time 7
tRC 50.625 ns
tRASmin 37.5 ns
tFAW 40.0 ns
Table 22: DDR3 SDRAM (PS) Parameters
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