Figure 12: Pull-Up During Configuration (PUDC) Resistors - Assembly Drawing Top and Bottom View (upper right and
upper left corners) for Revision 2 Modules
For details on the PUDC signal please refer to the Zynq-7000 All Programmable SoC Technical Reference
Manual [18].
3.3 Boot Mode
The boot mode can be selected via two signals available on the module connector.
Table 38 describes the available boot modes on the Mercury ZX1 SoC module.
BOOT_MODE1 BOOT_MODE0 Description
0 0 JTAG boot mode
0 1 Boot from NAND flash
1 0 Boot from QSPI flash
1 1 Boot from SD card
Table 38: Boot Modes
3.4 JTAG
The FPGA and the PS JTAG interfaces are connected into one single chain available on the module connector.
The SoC device, the QSPI flash, and the NAND flash can be configured via JTAG from Xilinx SDK or Xilinx
Vivado Hardware Manager.
D-0000-403-002 43 / 56 Version 05, 25.07.2019
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