The corresponding MIO pins are available on the module connector. Note that only MIO pins 40-45 allow the
Mercury ZX1 SoC module to boot from the SD card. Information on this boot mode is available in Section 3.6.
Please note that external pull-ups are needed for SD card operation. Depending on the selected voltage for
VCC_CFG_MIO_B12, a level shifter to 3.3 V may be required (some level shifters also have built-in pull-ups).
2.20 Gigabit Ethernet
A 10/100/1000 Mbit Ethernet PHY is available on the Mercury ZX1 SoC module, connected to the PS on MIO
pins 16-27.
Please note that Xilinx recommends operation at 1.8 V/2.5 V for the RGMII interface for the MIO pins [18].
Enclustra tests have shown that the RGMII is functional with a 3.3 V I/O voltage on the MIO pins, as long as
the I/O voltage configured in Vivado matches the applied I/O voltage.
2.20.1 Ethernet PHY Type
Table 29 describes the equipped Ethernet PHY device type on the Mercury ZX1 SoC module.
PHY Type Manufacturer Type
KSZ9031RNX Microchip (Micrel) 10/100/1000 Mbit
Table 29: Gigabit Ethernet PHY Type
2.20.2 Signal Description
The RGMII interface is connected to MIO pins 16-27 for use with the hard macro MAC. The interrupt output
of the Ethernet PHY is connected to an FPGA pin (K11).
The Gigabit Ethernet connections are presented in Table 30. All listed pins are operated at
VCC_CFG_MIO_B12 I/O voltage.
D-0000-403-002 36 / 56 Version 05, 25.07.2019
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