2.17.2 Signal Description
The QSPI flash is connected to the PS MIO pins 1-6. Some of the signals are available on the module con-
nector, allowing the user to program the QSPI flash from an external master.
Note that MIO pins 2-6 pins are shared between NAND flash and QSPI flash on the Mercury ZX1 SoC mod-
ule, therefore only of the two memories may be used at once. However, it is possible to switch between
them at runtime.
Please refer to Section 3 for details on programming the flash memory.
Warning!
Special care must be taken when connecting the QSPI flash signals on the base board. These signals
are shared with the NAND flash and have to be high impedance during normal operation.
Long traces or high capacitance may disturb the data communication between the SoC and the flash
devices.
2.17.3 Configuration
The QSPI flash supports up to 50 MHz operation for standard read. For fast, dual and quad read speed
values, please refer to the flash device datasheet.
Note that the “Feedback Clk” option on pin MIO8 must be enabled in the Zynq configuration for clock rates
higher than 40 MHz.
24-bit Address Compatibility Mode
If the Zynq device boots from the QSPI flash and the 24-bit address compatibility mode of the QSPI flash is
used to access the range above 16 MB, then the compatibility mode must be disabled before a system reset
is executed. Otherwise, the Zynq device will not be able to boot from the QSPI flash again, as the address
register is not pointing to the lower addressed part of the memory, in which the boot image is located.
The reset of the QSPI flash is connected to the PS_POR# power-on reset signal in order to avoid this issue
after a power-on reset. The PS_SRST# signal should not be used in this setup.
Please refer to Zynq-7000 Technical Reference Manual [18] for details on booting from the QSPI flash.
2.17.4 QSPI Flash Corruption Risk
There have been cases in which it was observed that the content of the flash device got corrupted. Ac-
cording to Cypress, this issue is caused by power loss during the Write Register (WRR) command. The most
common reason to use the WRR command is to turn the QUAD bit ON or OFF - this operation takes place
usually at the beginning of the boot process. If required, the bootloader code can be adjusted to set the
QUAD bit to a fixed value, without invoking this command during boot.
For additional information on this issue, please refer to the Cypress documentation and forum discussions
[26], [27].
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