Signal Name MIO Pin PL Pin
ETH_RST# PS_POR#
ETH0_INT# - K11
ETH_MDC MIO52
8
-
ETH_MDIO MIO53
8
-
ETH_RXC MIO22 -
ETH_RX_CTL MIO27 -
ETH_RXD0 MIO23 -
ETH_RXD1 MIO24 -
ETH_RXD2 MIO25 -
ETH_RXD3 MIO26 -
ETH_TXC MIO16 -
ETH_TX_CTL MIO21 -
ETH_TXD0 MIO17 -
ETH_TXD1 MIO18 -
ETH_TXD2 MIO19 -
ETH_TXD3 MIO20 -
Table 30: Gigabit Ethernet Signal Description
2.20.3 External Connectivity
The Ethernet signal lines can be connected directly to the magnetics. Please refer to the Enclustra Module
Pin Connection Guidelines [10] for details regarding the connection of Ethernet signals.
2.20.4 MDIO Address
The MDIO address assigned to the Gigabit Ethernet PHY is 3.
The MDIO interface is connected by default to MIO pins 52-53. These pins can also be used to access the
I2C bus - for details, please refer to Section 2.9.8.
2.20.5 PHY Configuration
The configuration of the Ethernet PHY is bootstrapped when the PHY is released from reset. Make sure all
I/Os on the RGMII interface are initialized and all pull-up or pull-down resistors are disabled at that moment.
The bootstrap options of the Ethernet PHY are set as indicated in Table 31.
Please note that the RGMII delays in the Ethernet PHY need to be configured before the Ethernet interface
can be used. This is done in the source files within the First Stage Boot Loader (FSBL) application provided
in the Mercury ZX1 SoC module reference design [2].
8
MIO52 and MIO53 can be used for either MDIO or I2C. Please refer to Section 2.9.8 for details.
D-0000-403-002 37 / 56 Version 05, 25.07.2019
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