REV.-A
2.3.3.2 E05A15HA Gate Array Functions
This gate array performs chip selection for the main components on the PEGX board, under the control
of the 78 10HG CPU. The gate array also outputs the lower address signals (AO through A7) for the ROM
and RAM using data from the CPU. In addition, the gate array controls the carriage motor and paper
feed motor, and drives the printhead and plunger solenoids.
Table 2-4 shows the pin assignments for the gate array. Refer to the Appendix for the details on the
gate array.
Table 2-4. Pin Function of GA (E05A15HA)
Pin No. Signal Name
Direction
Function
1
BANK O
OUT
Not used
2
BANK 1 OUT
3
CS4
OUT
Chip select signal for the gate array (7A):
Low active signal
4
CS3
OUT
Chip select signal for the ST-RAM (6A):
Low active signal
5
CS2 OUT
Chip select signal for the ST-RAM (5A):
Low active signal
6
Cs 1
OUT
Chip select signal for the P-RAM (4A):
Low active signal
7
P4
Not used
8
P3
IN
Home Position (HP) signal input
9
P2
IN
Paper End
(PE)
signal input
10
P1
IN
Friction/Tractor switch status input
Friction mode: High
Tractor mode: Low
11
Po
IN
Not
used
12 CRA
OUT
Carriage motor driving signal
13
CRB
OUT
14
CRC
OUT
15
CRD
OUT
16
HD 1
OUT
Printed driving signal
I I
(Head Data 1-8)
23
HD8
OUT
24
Vss
—
Logic Ground
25
Vss
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