GE ALPS - Page 7

GE Power Management
ALPS Advanced Line Protection System iii
TABLE OF CONTENTS
3. HARDWARE DESCRIPTION
3.1 CASE ASSEMBLY
3.1.1 CONSTRUCTION .............................................................................................. 3-1
3.1.2 ELECTRICAL CONNECTIONS AND WIRING .................................................. 3-3
3.1.3 IDENTIFICATION............................................................................................... 3-3
3.1.4 SYSTEM BLOCK DIAGRAM ............................................................................. 3-4
3.2 INSTALLATION
3.2.1 RECEIVING, HANDLING, AND STORAGE....................................................... 3-5
3.2.2 ENVIRONMENT................................................................................................. 3-5
3.2.3 MOUNTING........................................................................................................ 3-5
3.2.4 EXTERNAL CONNECTIONS............................................................................. 3-5
3.2.5 SURGE GROUND CONNECTIONS.................................................................. 3-5
3.3 PRINTED CIRCUIT BOARD MODULES
3.3.1 WARNING.......................................................................................................... 3-6
3.3.2 BASIC CONSTRUCTION ..................................................................................3-6
3.3.3 MODULE IDENTIFICATION .............................................................................. 3-6
3.3.4 LOCAL USER INTERFACE (LUI) ...................................................................... 3-6
3.3.5 INPUT BOARD................................................................................................... 3-6
3.3.6 MAGNETICS MODULE ..................................................................................... 3-8
3.3.7 COMMUNICATIONS INTERFACE .................................................................... 3-9
3.3.8 DIGITAL OUTPUT / POWER SUPPLY BOARD.............................................. 3-10
3.3.9 DSP / ANI / COMM / LUI.................................................................................. 3-11
3.3.10 960 CPU BOARD............................................................................................. 3-12
4. ACCEPTANCE/PERIODIC
TESTS
4.1 OVERVIEW
4.1.1 INTRODUCTION................................................................................................ 4-1
4.1.2 TEST EQUIPMENT............................................................................................ 4-1
4.1.3 DRAWINGS AND REFERENCES ..................................................................... 4-1
4.1.4 EQUIPMENT GROUNDING ..............................................................................4-2
4.1.5 REQUIRED SETTINGS ..................................................................................... 4-2
4.1.6 GENERAL INSTRUCTIONS..............................................................................4-2
4.1.7 SETTING CHANGES......................................................................................... 4-3
4.1.8 ENTERING TEST MODE................................................................................... 4-4
4.1.9 USING COMMUNICATIONS (OPTIONAL)........................................................ 4-4
4.2 GENERAL RELAY TESTS
4.2.1 T1 – RELAY STATUS AND DISPLAY TESTING............................................... 4-7
4.2.2 DISPLAY AND KEYPAD TESTS ....................................................................... 4-7
4.2.3 T2 – DIGITAL OUTPUT TEST........................................................................... 4-8
4.2.4 T3 – CONFIGURABLE INPUT AND OUTPUT TEST ........................................ 4-9
4.2.5 T4 – AC SYSTEM INPUT TEST ...................................................................... 4-10
5. FUNCTIONAL TESTS
(FACTORY SETTINGS)
5.1 TEST SUMMARY
5.1.1 DESCRIPTION................................................................................................... 5-1
5.2 MEASURING UNIT TESTS
5.2.1 T1 – FAULT DETECTOR TEST......................................................................... 5-2
5.2.2 T2 – IT TRIP SUPERVISION TEST................................................................... 5-2
5.2.3 T3 – IB BLOCKING SUPERVISION TEST ........................................................ 5-3
5.2.4 T4 – GROUND DIRECTIONAL TRIP TEST, IPT + NT...................................... 5-3
5.2.5 T5 – GROUND DIRECTIONAL BLOCK TEST, IPB + NB.................................. 5-3
5.2.6 T6 – PHASE INSTANTANEOUS OVERCURRENT 50 ..................................... 5-4
5.2.7 T7 – GROUND INSTANTANEOUS OVERCURRENT 50G...............................5-4
5.2.8 T8 – GROUND TIME OVERCURRENT 51G..................................................... 5-4
5.2.9 UNDERVOLTAGE TEST ................................................................................... 5-5
5.2.10 T9 – T10 – OVERVOLTAGE TEST ................................................................... 5-5
5.3 ZONE REACH AND TIMER TESTS
5.3.1 GENERAL ZONE REACH TESTING CONSIDERATIONS ............................... 5-8
5.3.2 T11 – ZONE 1 GROUND REACH, M1G GROUND FAULTS............................ 5-8
5.3.3 T12 – ZONE 2 GROUND REACH, MTG GROUND FAULTS............................ 5-9
5.3.4 T13 – ZONE 3 GROUND REACH, M3G GROUND FAULTS............................ 5-9
5.3.5 T14 - ZONE 4 GROUND REACH, M4G GROUND FAULTS........................... 5-10