GE Power Management ALPS Advanced Line Protection System E-
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APPENDIX E E.1 FIGURES AND TABLES
E
APPENDIX E FIGURES AND TABLESE.1 FIGURES AND TABLES E.1.1 LIST OF FIGURES
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ure 1–1: GROUND DISTANCE QUADRILATERAL CHARACTERISTIC ...................................................................................... 1-6
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ure 1–2: TENT CHARACTERISTIC............................................................................................................................................... 1-7
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ure 1–3: POTENTIAL FUSE FAILURE LOGIC DIAGRAMS........................................................................................................ 1-11
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ure 1–4: LINE PICKUP LOGIC DIAGRAM (THREE PHASE TRIPPING).................................................................................... 1-12
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ure 1–5: LINE PICKUP LOGIC DIAGRAM (SINGLE PHASE TRIPPING)................................................................................... 1-13
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ure 1–6: REMOTE-OPEN DETECTOR LOGIC (ROD)................................................................................................................ 1-14
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ure 1–7: OSB R-X DIAGRAM ...................................................................................................................................................... 1-15
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ure 1–8: OSB LOGIC DIAGRAMS............................................................................................................................................... 1-15
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ure 1–9: SWITCH SELECTION OF ACTIVE SETTING GROUP................................................................................................. 1-18
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ure 1–10: STEP DISTANCE LOGIC DIAGRAM .......................................................................................................................... 1-24
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ure 1–11: INTERCONNECTION DIAGRAM FOR PUTT/POTT WITH NS40A............................................................................ 1-25
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ure 1–12: PUTT LOGIC DIAGRAM.............................................................................................................................................. 1-26
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ure 1–13: PERMISSIVE OVERREACH TRANSFER TRIP (POTT1)........................................................................................... 1-28
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ure 1–14: POTT WITH BLOCKING FUNCTIONS (POTT2)......................................................................................................... 1-29
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ure 1–15: BLOCKING SCHEME LOGIC DIAGRAM.................................................................................................................... 1-31
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ure 1–16: INTERCONNECTION DIAGRAM FOR BLOCKING SCHEME WITH CS28A............................................................. 1-32
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ure 1–17: INTERCONNECTION DIAGRAM FOR BLOCKING SCHEME WITH CS61C............................................................. 1-32
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ure 1–18: HYBRID LOGIC DIAGRAM ......................................................................................................................................... 1-34
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ure 1–19: SINGLE PHASE TRIPPING LOGIC (EXCEPT FOR HYBRID SCHEME)................................................................... 1-35
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ure 1–20: SINGLE PHASE TRIPPING LOGIC (HYBRID SCHEME)........................................................................................... 1-36
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ure 1–21: OPEN POLE DETECTION LOGIC .............................................................................................................................. 1-37
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ure 1–22: INTER-CIRCUIT FAULT EXAMPLE............................................................................................................................ 1-38
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ure 1–23: OST MHO CHARACTERISTIC.................................................................................................................................... 1-42
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ure 1–24: OUT-OF-STEP TRIPPING LOGIC .............................................................................................................................. 1-42
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ure 1–25: COMPENSATED POSITIVE-SEQUENCE OVERVOLTAGE...................................................................................... 1-44
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ure 1–26: THREE-POLE TRIP ENABLE OUTPUT...................................................................................................................... 1-47
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ure 1–27: ELEMENTARY DIAGRAM WITH DEFAULT I/O (SINGLE PHASE TRIPPING).......................................................... 1-49
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ure 1–28: ELEMENTARY DIAGRAM WITH DEFAULT I/O (THREE PHASE TRIPPING)........................................................... 1-50
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ure 1–29: ELEMENTARY DIAGRAM (SINGLE PHASE TRIPPING)........................................................................................... 1-51
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ure 1–30: ELEMENTARY DIAGRAM (THREE PHASE TRIPPING)............................................................................................ 1-52
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ure 2–1: TRIP CIRCUIT MONITOR ............................................................................................................................................... 2-3
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ure 2–2: ALLOWABLE ZONE 1 REACH (WHEN USED WITH CVTs).......................................................................................... 2-9
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ure 2–3: POWER SYSTEM ONE LINE DIAGRAM WITH SERIES CAPACITORS ..................................................................... 2-10
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ure 2–4: TENT CHARACTERISTIC............................................................................................................................................. 2-12
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ure 2–5: MAXIMUM ALLOWABLE REACH ................................................................................................................................. 2-13
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ure 2–6: OPERATING TIME CHARACTERISTIC........................................................................................................................ 2-14
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ure 2–7: MODIFIED GDOC LOGIC, MHO2GDOC ...................................................................................................................... 2-15
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ure 2–8: GROUND DISTANCE FUNCTION CHARACTERISTIC................................................................................................ 2-18
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ure 2–9: R-X DIAGRAM FOR ZONE 4 DISTANCE FUNCTIONS ............................................................................................... 2-18
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ure 2–10: ZONE 4 FAULT EXAMPLE.......................................................................................................................................... 2-19
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ure 2–11: NT/NB FUNCTIONS.................................................................................................................................................... 2-24
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ure 2–12: ROD LOGIC DIAGRAM............................................................................................................................................... 2-31
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ure 2–13: TL5PICKUP / TL6PICKUP REPRESENTATION......................................................................................................... 2-35
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ure 2–14: OSB FUNCTION CHARACTERISTIC ......................................................................................................................... 2-38
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ure 2–15: OST CHARACTERISTIC............................................................................................................................................. 2-39
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ure 2–16: OST REACH CHARACTERISTIC ............................................................................................................................... 2-40
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ure 2–17: OUT OF STEP TRIPPING LOGIC............................................................................................................................... 2-41
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ure 2–18: INVERSE CURVE........................................................................................................................................................ 2-48
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ure 2–19: VERY INVERSE CURVE............................................................................................................................................. 2-49
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ure 2–20: EXTREMELY INVERSE CURVE................................................................................................................................. 2-50
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ure 3–1: DIMENSIONS .................................................................................................................................................................. 3-1
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ure 3–2: FRONT AND REAR VIEW............................................................................................................................................... 3-2
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ure 3–3: CIRCUIT BOARD LOCATIONS....................................................................................................................................... 3-3
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ure 3–4: ALPS SYSTEM BLOCK DIAGRAM................................................................................................................................. 3-4
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ure 3–5: INPUT BOARD DIAGRAM............................................................................................................................................... 3-7
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ure 3–6: BLOCK DIAGRAM OF THE MAGNETICS MODULE......................................................................................................3-8
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ure 3–7: BLOCK DIAGRAM OF THE COMMUNICATIONS MODULE.......................................................................................... 3-9
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ure 3–8: BLOCK DIAGRAM OF THE DIGITAL OUPUT / POWER SUPPLY .............................................................................. 3-10
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ure 3–9: BLOCK DIAGRAM OF THE DSP / COMM / LUI MODULE........................................................................................... 3-11
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ure 3–10: BLOCK DIAGRAM OF THE SYSTEM PROCESSOR (i960 CPU) .............................................................................. 3-12
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ure 4–1: DIGITAL OUTPUTS TEST CONNECTIONS................................................................................................................... 4-9
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ure 4–2: CONFIGURABLE INPUT/OUTPUT TEST CONNECTIONS ......................................................................................... 4-11
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