Intel® Server Board S5500WB TPS Functional Architecture
Revision 1.3
Intel order number E53971-004
21
PCI Express*, PCI-X*, PCI (including peer-to-peer communication support), AGP (Accelerated
Graphics Port), and so forth, through the appropriate bridges.
Each Intel
®
QPI link consists of 20 pairs of uni-directional differential lanes for the transmitter
and receiver plus a differential forwarded clock. A full-width Intel
®
QPI link pair consists of 84
signals (20 differential pairs in each direction) plus a forwarded differential clock in each
direction. Each Intel
®
5500 series processor supports two Intel
®
QPI links, one going to the
second processor and one going to the Intel
®
5500 chipset IOH.
Figure 15. Intel
®
QPI Link
In the current implementation, Intel
®
QPI ports are capable of operating at transfer rates of up to
6.4 GT/s. Intel
®
QPI ports operate at multiple lane widths (full - 20 lanes, half - 10 lanes, and
quarter - 5 lanes) independently in each direction between a pair of devices communicating via
the Intel
®
QPI. The server boards support full-width communication only.
For more information see the Intel
®
QPI Overview Rev 1.04 (Document#: 380531)
3.4 Intel
®
QuickPath Memory Controller
The Intel
®
5500 series processor has an integrated memory controller on its package. Each
Intel
®
5500 Series processor produces up to three channels of DDR3 memory. The Intel
®
QPI
Memory Controller supports DDR3 800, DDR3 1066, and DDR3 1333 memory technologies.
The memory controller supports both Registered DIMMs (RDIMMs) and Unbuffered DIMMs
(UDIMMs).
Mixing of RDIMMs and UDIMMs is not supported.
3.4.1 Supported Memory
The Intel
®
Server Board S5500WB supports six DDR3 memory channels (three per processor
socket) with two DIMMs on the first channel and one DIMM on the second and third channels of
each processor. Therefore, the server board supports up to 8 DIMMs with dual-processor
sockets with a maximum memory capacity of 64 GB.
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