Intel S5500WB User Manual

Intel® Server Board S5500WB TPS Platform Management Features
Revision 1.3
Intel order number E53971-004
43
• Wake IPMI command is supported (BMC function no additional hardware requirement)
for all supported Sleep states.
5.5.2 PCI Express* Power management
L0 and L3 power management states are supported on all PCI Express* slots and embedded
end points.
5.5.3 PMBus*
Power supplies that have PMBus* 1.1 are supported and required to support Intel
®
Dynamic
Power Node Manager. Intel
®
Server Board S5500WB supports the features of Intel
®
Dynamic
Power Node Manager version 1.5 except the inlet temperature sensor.
5.6 SMBUS Architecture Block
Figure 20.
S5500WB SMBUS Block Diagram
5.6.1 SMBUS Device Addresses
Table 21 lists the SMBus addresses of various devices by bus.
Table 15. SMBus Device Address Assignment
Main
Bus
Power
Rail
Sub
Bus
Power
Rail
Device SMBus
Address
Note
IBMC SMBus 3 No Connect
ICH10R SMBus 0x88
CK509B 0xD2
NA NA
DB403 0xDC
Host 3V3SB
Host 3V3 XDP

Intel S5500WB Specifications

General

Brand	Intel
Model	S5500WB
Category	Server Board
Language	English