Functional Architecture Intel® Server Board S5500WB TPS
Revision 1.3
Intel order number E53971-004
22
The server board supports DDR3 800, DDR3 1067, and DDR3 1333 memory technologies.
Memory modules of mixed speed are supported by automatic selection of the highest common
frequency of all memory modules.
The following configurations are not supported, validated or recommended:
• Mixing of RDIMMs and UDIMMs is not supported
• Mixing of memory type, size, speed and/or rank has not been validated and is not supported
• Mixing memory vendors has not been validated and is not recommended
• Non-ECC memory has not been validated and is not supported in a server environment
NOTE: Mixed memory is not tested or supported. Non-ECC memory is not tested and is not
recommended for use in a server environment
The Intel
®
Server Board S5500WB uses a 2:1:1 memory DIMM layout. A 2:1:1 layout was
chosen for its lowest power for a particular bandwidth and because it allows the maximum
possible bandwidth when a 1:1:1 memory population is used.
3.4.2 Memory Subsystem Nomenclature
DIMMs are organized into physical slots on DDR3 memory channels that belong to processor
sockets.
The memory channels from socket 1 are identified as Channels A, B, and C. The memory
channels from socket 2 are identified as Channels D, E, and F.
The DIMM identifiers on the silkscreen on the board provide information about the channel, and,
therefore the processor, to which they belong. For example, DIMM_A1 is the first slot on
Channel A on processor 1; DIMM_D1 is the first DIMM socket on Channel D on processor 2.
Table 5. DIMM Nomenclature
Processor Socket 1 Processor Socket 2
Channel A Channel B Channel C Channel D Channel E Channel F
A1 A2 B1 C1 D1 D2 E1 F1
If the socket is not populated, the memory slots associated with a processor socket are
unavailable.
You can install a processor without populating the associated memory slots provided a second
processor is installed with associated memory. In this case, the memory is shared by the
processors. However, the platform suffers performance degradation and latency due to the
remote memory.
Sockets are self-contained and autonomous. However, all configurations in the BIOS setup
such as RAS, Error Management, and so forth, are applied commonly across sockets.
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